CQRS12
CQRS12 - Device Queue Status
| Module Instance | Base Address | Register Address |
|---|---|---|
i_sdmmc__sdmmc_apb_slv__10808000____CQRS____SEG_L4_MP_sdmmc_s_0x0_0x1000
|
0x10808400
|
0x10808430
|
Size: 32
Offset: 0x30
Access: RO
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
|
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
|
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CQRS12 Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 31:0 |
CQDQS
|
CQDQS - Device Queue Status\n
This register reflects to eMMC device status. Task N is ready for execution when bit N in this register is set to 1.
This register is updated each time response for SEND_QUEUE_STATUS (CMD13) is received.
|
RO
|
0x0
|