CQRS06 

         
            CQRS06 - Command Queuing Interrupt Signal Enable\n
            This register allows to turn on or turn off interrupt notification separately
            for each bit of the Command Queuing Interrupt Status.  When Interrupt status bit
            is set 1 and related field in this register is set (S/W wrote 1 to the filed),
            the Interrupt Status is reported on interrupt port.
Module Instance Base Address Register Address
i_sdmmc__sdmmc_apb_slv__10808000____CQRS____SEG_L4_MP_sdmmc_s_0x0_0x1000 0x10808400 0x10808418

Size: 32

Offset: 0x18

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_4

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_4

RO 0x0

CQTCLSI

RW 0x0

CQREDSI

RW 0x0

CQTCCSI

RW 0x0

CQHACSI

RW 0x0

CQRS06 Fields

Bit Name Description Access Reset
31:4 Reserved_4 
Reserved bitfield added by Magillem
 RO 0x0
3 CQTCLSI 
              CQTCLSI - Task Cleared Signal Enable (TCL)\n
              Enables interrupt signaling from CQTCL register.
RW 0x0
2 CQREDSI 
              CQREDSI - Response Error Detected Signal Enable (TCC)\n
              Enables interrupt signaling from CQREDI register.
RW 0x0
1 CQTCCSI 
              CQTCCSI - Task Complete Signal Enable (TCC)\n
              Enables interrupt signaling from CQTCC register.
 RW 0x0
0 CQHACSI 
              CQHACSI - Halt Complete Signal Enable (HAC)\n
              Enables interrupt signaling from CQHLT register.
RW 0x0