CQRS04 

         
            CQRS04 - Command Queuing Interrupt Status\n
            This register has several status bit related to specific interrupt event.
            When even happened and related Command Queuing Interrupt Status Enable is set, the status bit is set to 1.
            The bits can be cleared by S/W.\n
            Write 0 clears bit.\n
            Write 1 is ignored.
Module Instance Base Address Register Address
i_sdmmc__sdmmc_apb_slv__10808000____CQRS____SEG_L4_MP_sdmmc_s_0x0_0x1000 0x10808400 0x10808410

Size: 32

Offset: 0x10

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_4

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_4

RO 0x0

CQTCL

RW 0x0

CQREDI

RW 0x0

CQTCC

RW 0x0

CQHAC

RW 0x0

CQRS04 Fields

Bit Name Description Access Reset
31:4 Reserved_4 
Reserved bitfield added by Magillem
 RO 0x0
3 CQTCL 
              CQTCL - Task Cleared (TCL)\n
              When task clear operation or clear individual task is completed, the CQE sets this bit to 1.
RW 0x0
2 CQREDI 
              CQREDI - Response Error Detected Interrupt (RED)\n
              When an error is detected in the response received from eMMC device, the CQE sets this bit to 1.
              S/W can select which bits are analyzed by selecting CQRMEM.
RW 0x0
1 CQTCC 
              CQTCC - Task Complete Interrupt (TCC)\n
              CQE sets this bit when either a task with INT=1 is completed or Interrupt Coalescing reports interrupt.
RW 0x0
0 CQHAC 
              CQHAC - Halt Complete Interrupt (HAC)\n
              CQE sets this bit when value of CQHLT changed from 0 to 1.
RW 0x0