CQRS16 

         CQRS16 - Send Status Configuration 1
Module Instance Base Address Register Address
i_sdmmc__sdmmc_apb_slv__10808000____CQRS____SEG_L4_MP_sdmmc_s_0x0_0x1000 0x10808400 0x10808440

Size: 32

Offset: 0x40

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_2

RO 0x0

CQSSCBC

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CQSSCIT

RW 0x0

CQRS16 Fields

Bit Name Description Access Reset
31:20 Reserved_2 
Reserved bitfield added by Magillem
 RO 0x0
19:16 CQSSCBC 
              CQSSCBC - Send Status Command Block Counter (CBC)\n
              S/W can define if and when CQE sends SEND_QUEUE_STATUS (CMD13) command during data transfer.\n
              When this register is set 0, the CQE does not send CMD13 during data transfer.
              The value is 1, 2, or N means, the CQE sends CMD13 is transferred during last, one before last, or (N-1) before last block, respectively.\n
              Accepted register value range is 0 to 15.
RW 0x0
15:0 CQSSCIT 
              CQSSCIT - Send Status Command Idle Timer (CIT)\n
              When CQE is in idle, the host controller can poll device by sending SEND_QUEUE_STATUS (CMD13) with interval defined by this register.
              Accepted register value is in range 1 to 65535.
              The interval can be calculated as CQSSICT * internal clock period.
RW 0x0