CQRS14 

         
            CQRS14 - Task Clear\n
            S/W writes 1 to N bit of this register to clear task N.
            Bit remains 1 until clear operation is completed. Once operations ends, the CQE clears this bit to 0.
            The S/W has to ensure the CQ Engine is halted before clearing tasks.
            The S/W can clear only single task.  When any bit of this register is set, the
            S/W has no to request new task clear. This operation clears only task in the Host Controller.
            The S/W should take care about clearing task in the device.\n
            Writing 0 to register is ignored.
Module Instance Base Address Register Address
i_sdmmc__sdmmc_apb_slv__10808000____CQRS____SEG_L4_MP_sdmmc_s_0x0_0x1000 0x10808400 0x10808438

Size: 32

Offset: 0x38

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CQTC31

RW 0x0

CQTC30

RW 0x0

CQTC29

RW 0x0

CQTC28

RW 0x0

CQTC27

RW 0x0

CQTC26

RW 0x0

CQTC25

RW 0x0

CQTC24

RW 0x0

CQTC23

RW 0x0

CQTC22

RW 0x0

CQTC21

RW 0x0

CQTC20

RW 0x0

CQTC19

RW 0x0

CQTC18

RW 0x0

CQTC17

RW 0x0

CQTC16

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CQTC15

RW 0x0

CQTC14

RW 0x0

CQTC13

RW 0x0

CQTC12

RW 0x0

CQTC11

RW 0x0

CQTC10

RW 0x0

CQTC09

RW 0x0

CQTC08

RW 0x0

CQTC07

RW 0x0

CQTC06

RW 0x0

CQTC05

RW 0x0

CQTC04

RW 0x0

CQTC03

RW 0x0

CQTC02

RW 0x0

CQTC01

RW 0x0

CQTC00

RW 0x0

CQRS14 Fields

Bit Name Description Access Reset
31 CQTC31 
CQTC31 - Command Queuing Task Clear #31
RW 0x0
30 CQTC30 
CQTC30 - Command Queuing Task Clear #30
RW 0x0
29 CQTC29 
CQTC29 - Command Queuing Task Clear #29
RW 0x0
28 CQTC28 
CQTC28 - Command Queuing Task Clear #28
RW 0x0
27 CQTC27 
CQTC27 - Command Queuing Task Clear #27
RW 0x0
26 CQTC26 
CQTC26 - Command Queuing Task Clear #26
RW 0x0
25 CQTC25 
CQTC25 - Command Queuing Task Clear #25
RW 0x0
24 CQTC24 
CQTC24 - Command Queuing Task Clear #24
RW 0x0
23 CQTC23 
CQTC23 - Command Queuing Task Clear #23
RW 0x0
22 CQTC22 
CQTC22 - Command Queuing Task Clear #22
RW 0x0
21 CQTC21 
CQTC21 - Command Queuing Task Clear #21
RW 0x0
20 CQTC20 
CQTC20 - Command Queuing Task Clear #20
RW 0x0
19 CQTC19 
CQTC19 - Command Queuing Task Clear #19
RW 0x0
18 CQTC18 
CQTC18 - Command Queuing Task Clear #18
RW 0x0
17 CQTC17 
CQTC17 - Command Queuing Task Clear #17
RW 0x0
16 CQTC16 
CQTC16 - Command Queuing Task Clear #16
RW 0x0
15 CQTC15 
CQTC15 - Command Queuing Task Clear #15
RW 0x0
14 CQTC14 
CQTC14 - Command Queuing Task Clear #14
RW 0x0
13 CQTC13 
CQTC13 - Command Queuing Task Clear #13
RW 0x0
12 CQTC12 
CQTC12 - Command Queuing Task Clear #12
RW 0x0
11 CQTC11 
CQTC11 - Command Queuing Task Clear #11
RW 0x0
10 CQTC10 
CQTC10 - Command Queuing Task Clear #10
RW 0x0
9 CQTC09 
CQTC09 - Command Queuing Task Clear #09
RW 0x0
8 CQTC08 
CQTC08 - Command Queuing Task Clear #08
RW 0x0
7 CQTC07 
CQTC07 - Command Queuing Task Clear #07
RW 0x0
6 CQTC06 
CQTC06 - Command Queuing Task Clear #06
RW 0x0
5 CQTC05 
CQTC05 - Command Queuing Task Clear #05
RW 0x0
4 CQTC04 
CQTC04 - Command Queuing Task Clear #04
RW 0x0
3 CQTC03 
CQTC03 - Command Queuing Task Clear #03
RW 0x0
2 CQTC02 
CQTC02 - Command Queuing Task Clear #02
RW 0x0
1 CQTC01 
CQTC01 - Command Queuing Task Clear #01
RW 0x0
0 CQTC00 
CQTC00 - Command Queuing Task Clear #00
RW 0x0