1. Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide
This user guide provides a brief overview of the various tabs in the
device-specific PDN tool 2.0. It provides conceptual information and is common for all
devices. You can quickly and accurately design a robust power delivery network with the PDN
tool 2.0. This is done by calculating an optimum number of capacitors that meet the target
impedance requirements for a given power supply.
Note: The PDN tool 2.0 only supports Microsoft Excel 2007 and newer, and either US or UK English language.
Table 1. PDN Tool 2.0 Software VerificationIntel has tested and verified that the PDN tool 2.0 is
compatible with these platforms and software versions.
Windows 10 Professional (64-bit)
Office 2010 and 2016
Windows 8.1 Professional (32-bit)
Office 2007, 2010, and 2013
Windows 8.1 Professional (64-bit)
Office 2010 and 2013
Windows 7 (64-bit)
PDN tool 2.0 helps PCB designers estimate the number, value, and type of decoupling capacitors
needed to develop an efficient PCB decoupling strategy. It allows you to do this during the
early design phase, without going through extensive pre-layout simulations.
The PDN tool 2.0 is a Microsoft Excel-based spreadsheet that calculates an
impedance profile based on your input. For a given power supply, the spreadsheet only requires
basic design information to calculate the impedance profile and the optimum number of
capacitors to meet the desired impedance target (ZTARGET). Basic
design information includes the board stackup, transient current information, and ripple
specifications, for example. The tool also provides the device- and power rail-specific PCB
decoupling cut-off frequency (FEFFECTIVE). The results obtained
through the PDN tool 2.0 are intended only as a preliminary estimate and not as a
specification. For an accurate impedance profile, Intel recommends a post-layout simulation approach using any available EDA
tool, such as Cadence PowerSI, Ansys SIWave, and Cadence Allegro PCB PI.
There are two versions of the PDN tool 2.0. One version is for 20-nm devices
(which also includes the 14-nm
Stratix® 10 devices), and one
version is for all other devices listed below. The device families supported by the Intel device-specific PDN tool 2.0 are shown at the top of
the Release Notes tab and they include:
The PDN tool 2.0 provides two parameters for guiding PCB decoupling design: ZTARGET and FEFFECTIVE.
1.2.1. PDN Circuit Topology
The PDN tool 2.0 is based on a lumped equivalent model representation of the power delivery network topology.
Figure 1. PDN Topology Modeled as Part of the Tool The PDN impedance profile is the impedance-over-frequency looking outward from
For a first order analysis, the VRM can be simply modeled as a series-connected
resistor and inductor as shown above. This is a result of the typical proportional, integral,
derivative (PID) voltage regulation loop compensation configuration of many regulators. The
VRM has a very low impedance and can respond to the instantaneous current requirements of the
FPGA up to between 50 kHz and 150 kHz, depending on the voltage regulation loop crossover (0
The equivalent series resistance (ESR) and equivalent series inductance (ESL)
values can be obtained from the VRM manufacturer. At higher frequencies, the VRM impedance is
primarily inductive, making it incapable of meeting the transient current requirement.
PCB decoupling capacitors are used for reducing the PDN impedance up to 50-100
MHz. The on-board discrete decoupling capacitors provide the required low impedance. This
depends on the capacitor-intrinsic parasitics (RcN, CcN, LcN) and the capacitor mounting
inductance (LmntN). The inter-planar capacitance between the
power-ground planes typically has lower inductance than the discrete decoupling capacitor
network, making it more effective at higher frequencies up to 100 MHz. As frequency increases,
the PCB decoupling capacitors become less effective. The limitation comes from the parasitic
inductance seen with respect to the FPGA. FPGA parasitic inductance includes capacitor
mounting inductance, PCB spreading inductance, ball grid array (BGA) via inductance, and
packaging parasitic inductance. All of these parasitics are modeled in the PDN tool 2.0 to
capture the effect of the PCB decoupling capacitors accurately. To simplify the circuit
topology, all parasitics are represented with lumped inductors and resistors despite the
distributed nature of PCB spreading inductance.
The change of dynamic component of PDN current gives rise to voltage
fluctuation within the PDN, which may lead to logic and timing issues. You can reduce
excessive voltage fluctuation by reducing PDN impedance. One design guideline is target
impedance, ZTARGET. In the frequency domain, voltage
fluctuation across a circuit at a frequency is proportional to the current flow through
the circuit, and the impedance of the circuit at the frequency according to Ohm’s law.
ZTARGET is defined using the maximum allowable noise
tolerance and dynamic current change, and is calculated as follows.
Figure 2. ZTARGET Equation
For example, the dynamic current of a 1.8 V power rail is 2 A. The worst case
dynamic current change is 50% of the dynamic current. The noise tolerance of the power
rail is 5% of the nominal voltage. The desired PDN target impedance for decoupling
design is calculated as follows:
Figure 3. ZTARGET Example Equation
To accurately calculate the ZTARGET for any power rail, you
must know the following information:
The maximum dynamic current change requirements for the FPGA that is powered by
the power rail under consideration. You can obtain this information from respective
device datasheet. You can calculate the maximum dynamic current change of a device
using the maximum dynamic current and the dynamic current change percentage.
Note: The dynamic
current is intended to parameterize the high-frequency current draws required to
provide the energy for CMOS transistors changing state. In the case of the core
rail, the transients are generated by switching inside the FPGA core. Thus, a
design which involves extensive logical switching generates higher % transients
(dynamic current change) than a more static design. The dynamic current change
be higher if the dynamic current is higher. For information
about default settings of the dynamic current change percentage for major FPGA
rails, refer to the table in the Introduction tab of the PDN tool 2.0.
Note: You can obtain
accurate estimations on the maximum dynamic current for
Intel® FPGA devices using the Early Power
Estimator (EPE) tool or the
tools. When using the data from the EPE, be sure to use only the dynamic power
for each section for the PDN calculation.
The maximum allowable noise tolerance
on the power rail is given as a percentage of the supply voltage.
Device switching activity leads to transient noise (high frequency spikes)
seen on the power supply rails. This noise can cause functionality issues if they are
too high. The noise must be damped within a range defined as a percentage of power
supply voltage. The recommended values for the maximum allowable noise tolerance are
listed in the respective device datasheet and in the Introduction tab of the PDN tool 2.0. Different rails have different
specifications because of their sensitivity to the transient voltage noise as well as
how much current is used by the power rail.
Refer to the Introduction tab of the PDN tool 2.0 for more
information about ZTARGET.
Table 2. Settings for the
Stratix® 10 Device Power
RailsThis information is from the PDN tool 2.0 for a
Stratix® 10 device.
If each VCCIO_UIB (BL or TL) is individually
designed, use 100% of the total dynamic current.
If both VCCIO_UIBs (BL and TL) are combined:
If both HBM operations are coherent,
use 100% of the total dynamic current.
If both HBM operations are
non-coherent, use 71% of the total dynamic current.
The FEFFECTIVE for
VCCIO_UIB at package level is 2 MHz to meet target
As previously described, a capacitor reduces PDN impedance by providing a
least-impedance route between power and ground for transient current. Impedance of a
capacitor at high frequency is determined by its parasitics (ESL and ESR). For a PCB
with capacitors mounted, the parasitics include not only the parasitic from the
capacitors themselves but also those associated with mounting, PCB spreading, and
packaging. Therefore, PCB capacitor parasitics are generally higher than on-die
capacitor parasitics. As a result, decoupling using PCB capacitors becomes ineffective
at higher frequencies. Using PCB capacitors for PDN decoupling beyond their effective
frequency range brings no improvement to PDN performance and raises the bill of
materials (BOM) cost.
To help reduce over-design of PCB decoupling, this release of the PDN tool
provides a suggested PCB decoupling design cut-off frequency (FEFFECTIVE) as another guideline. You only need to design PCB decoupling that
keeps ZEFF under ZTARGET up to
FEFFECTIVE. ZEFF is the
impedance profile of the PCB design and includes all PDN-related design parasitics,
VRM R and L
PCB spreading R and L
Plane R and C
BGA_via R and L
FEFFECTIVE defines the effective frequency of
on-board decoupling capacitors.
Refer to Troubleshooting ZEFF
if the ZEFF is
too high or the number of capacitors for decoupling becomes too high.
Note: FEFFECTIVE may not
be enough when the Intel FPGA device shares a power rail with
another device. The noise generated from other devices propagates along the PDN and
affects FPGA device performance. The frequency of the noise is determined by the
transfer impedance between the noise source and the FPGA device, and can be higher than
FEFFECTIVE. Reducing PDN parasitic inductance and
increasing the isolation between the FPGA device and noise source reduces this risk. You
must perform a transfer impedance analysis to clearly identify any noise interference
The tabs at the bottom of the PDN tool 2.0 application help you calculate your impedance profile.
Table 3. PDN Tool 2.0 Tabs
legal disclaimers, the revision history of the tool, and the user
Displays the schematic representation of the circuit that is modeled as part of the PDN tool 2.0. It also provides the following related information:
quick start instructions
settings for some power rails
a brief description of decoupling design procedures under
different power supply connection schemes
The principal tab that allows you to decouple your system. It displays by default when you launch the application. This tab provides an interface to enter your power sharing scheme for a selected FPGA device and derive the decoupling based on the input.
Provides an interface to enter your stackup information into the PDN tool.
Points to various libraries (capacitor, dielectric materials, and so on) that are called by other tabs. You can change the default values listed as part of these libraries.
Provides an interface to calculate the BGA mounting inductance based on design-specific via parameters and the number of vias.
Provides an interface to calculate the plane capacitance based on design-specific
Provides an interface to input design-specific parameters for calculating the capacitor mounting inductance for two different capacitor orientations (Via on Side [VOS] and Via on End [VOE]).
Provides an interface to input design-specific parameters for calculating the capacitor mounting inductance for X2Y type capacitors.
Provides an enlarged view of the Z-profile shown in the System_Decap tab.
You can determine the decoupling of selected FPGA devices based on the power
sharing scheme entered in the System_Decap tab.
The System_Decap tab is divided into the following sections:
Power rail data and configuration
Rail group summary
22.214.171.124.1. Device Selection Section
Select the Family/Device using the
In the 20-nm Pro version of the PDN tool, choose
Cyclone® 10 GX devices. In the 20 nm Standard version of the tool,
MAX® 10 devices. In the 28 nm PDN tool, choose
all other devices.
Select your device
and the package type
from the Available Devices
Select your desired power rail configuration from the Power Rail Configuration
Power Rail Configuration list includes custom and
pre-defined configurations. When you select a pre-defined configuration, the tool sets the
suggested power rail grouping automatically.
The drop-down selections are based on examples from the pin connection
guidelines for the device. Select the one that most closely matches your design, and use it as
a basis for entering your design data. Refer to the pin connection guidelines for your
The tool updates the list of power rails and the contents in the power rail
configuration sections based on your selections.
126.96.36.199.2. Power Rail Data and Configuration Section
This section of the application is divided into two areas. Area 1 is for the device power rail information, and Area 2 is for the power rail configuration.
the power supply voltage in the Voltage
column for each power rail listed in Area 1 by selecting a value from the
pull-down menu, or by manually entering your own
Note: You must enter the total
dynamic current consumption of related power rails before you can use the
system decoupling function.
You can optionally adjust the recommended number up or down
slightly based on knowledge of the intended application.
Enter the current consumption in the Imax
column for each power rail.
The earliest data from the Early Power Estimator (EPE)
can provide good values for the current entries. The EPE delivers bulk data for
the transceiver channels. Each bank of transceiver channels should be assigned
the total EPE value divided by the number of banks. Later in the design cycle,
power analyzer can derive much better data for each bank rail.
Setup your device power sharing scheme in Area 2.
Figure 6. Power Rail Data and Power Sharing Scheme
SectionThis configuration is an example of how this section of the spreadsheet
should look. Every
depending on the device chosen and the power rail configuration
The current usage for each rail should be entered in the
Imax (Maximum Dynamic
Current) column in Area 1. Note that, for the
VCC rail, only the dynamic current usage should be entered from the Early
Each column in Area 2 represents a power group in your system. Add or
remove a power group using the Add Group or Remove Group buttons. The first row
of each group is the
Regulator/Separator type. Set the source type
for the power group and available options from the pull-down list as switcher,
linear, or filter.
The second row is the
Parent Group type. The available options for
this row are
None and the number representing all listed
power groups. Input your power sharing
hierarchy in this column, and set the power rail connection using the remaining rows.
Note: The PDN tool 2.0 defines
the power rail configuration using the Parent/Child power group. A power group is a child power
group if it attaches to another power group at its input. The other power
group is the parent group in this case. A parent group can have multiple
child groups. A parent power group number is required for the child group.
The parent group number of a parent power group is assigned to None because the group has no parent group.
The available Area 2 rail options are:
blank — Device rail does not connect to the power group.
Device rail connects to the power group.
Device rail connects to the group, and its activity is related to other rails
that connect to the same group. You must select
x/related if that VCCIO/VCCPT power rail is
related to other rails within the same power rail group.
Note: Two I/O rails are related
if their output activities are synchronous. For example, when two VCCIO
rails are assigned to the same memory interface. The maximum current
at the same time for these related rails. As a result, the total current of
related rails equals the sum of the current of all shared rails. The total
current of unrelated rails is calculated using the root-sum-square (RSS)
The PDN tool 2.0 sets the default power rail sharing configuration based on the
selected Intel-recommended power rail
configuration listed above. Make changes to better match your design.
In the rail connection matrix, you can change the
voltage of a rail without disconnecting it from a regulator group.
However, all other rails connected to the same group must be able to change to the new voltage.
Figure 7. Changing Voltage for All Rails in a
188.8.131.52.3. Meeting Target Impedance when Entering 0 mA into the PDN Tool
You may not be able to meet the target impedance if you enter 0 mA
Intel® Power Distribution Network
If you enter 0 mA into some low current power supply pin types, such
as VCCBAT, the PDN tool calculates a high effective
impedance. Other power supply pin types may also show this problem.
The minimum allowable non-zero current entry into the Intel PDN Tool
is 0.001 mA. If you enter 0 mA for currents below 0.001 mA, a divide-by-zero or
multiply-by-zero problem can occur.
To avoid this problem, enter 0.001 mA to calculate decoupling for
currents less than 0.001 mA. Entering 0.001 mA does not significantly burden the
184.108.40.206.4. Dealing with Multiple Shared Power Supply Pin Types
You cannot add currents from multiple shared power supply pin
types and enter them into a single supply pin type using the
Intel® Power Distribution Network (PDN) tool.
The PDN tool calculates
effective impedance based on the number of pins and package parasitic information
for the chosen device. Entering the sum of shared currents into a single power
supply pin type causes the PDN tool to miscalculate the spreading inductance. You
should always enter the correct current for each power supply pin type into the PDN
shared 1.2 V power supply consists of VCCIO2A and VCCIO2B, each drawing 0.3 A for a total of 0.6 A, you
should not enter 0.6 A for VCCIO2A and 0 A for VCCIO2B.
Instead, you should enter 0.3 A for VCCIO2A and 0.3 A for VCCIO2B.
If a shared 1.03
V power supply consisting of VCCR_GXBL1C, VCCR_GXBL1D, VCCT_GXBL1C, and
VCCT_GXBL1D drawing 0.5 A, 0.5 A, 0.2 A, and 0.2 A
respectively, you should not enter 1 A for VCCR_GXBL1C and 0.4 A for VCCT_GXBL1C.
Instead, you should enter VCCR_GXBL1C = 0.5 A, VCCR_GXBL1D
= 0.5 A, VCCT_GXBL1C = 0.2 A, and VCCT_GXBL1D = 0.2 A.
220.127.116.11.5. VRM Data Section
Enter the voltage regulator module (VRM) parameters for DC supply voltage, Switcher VRM
Efficiency, and Switcher VRM Input
Note: If you are
using a VRM with a sense line, the system compensates for the IR drop
18.104.22.168.6. Rail Group Summary Section
In this section, you can find a list of the following calculated key
parameters of all power groups:
Dynamic Current Change
Core Clock Frequency
Current Ramp Up Period
These options allow you to customize how the data is collected or
The Dynamic Current Change parameter has
a pull-down menu with the following options:
Dynamic current change percentage requires a lot of diligence. The EPE and
analyzer both deliver values for current usage that include:
the maximum static current (does not vary)
the maximum current usage by the active elements
This calculation yields both a very high total current and a fairly high
dynamic current usage. Calculations for a value to insert into the Dynamic Current Change field
yield a value much lower than the auto-populated value, which
represents a safe engineering value.
The Noise Tolerance parameter has a
pull-down menu with the following options:
Some PDN tool variants allow you to add data for the Core Clock Frequency and Current Ramp Up
Period parameters using the pull-down menus. These values tell the tool
how to calculate the current ramp up period for transient events, sometimes reducing
transient current changes. The values relate to how fast the clock for the section is
running, and the length of the data pipeline. Given a transient change in the input
data, there are clock cycles in the pipeline for the algorithm to deliver the results.
If the input data change activates a broad yet short pipeline, the transient is abrupt.
This results in a large current change for the number of logic elements being used. If
the pipeline is narrow and long, the overall change in current usage is proportionately
You can set the Core Clock Frequency parameter to a
Low, or Custom set of input
frequencies. The Custom option allows you to enter a specific
The Current Ramp Up Period parameter
allows you to specify the number of clock cycles consumed by the pipeline. You can
select a Long, Medium, Short, or Custom setting.
Core Clock Frequency and Current Ramp Up
Period options are highly dependent upon the core utilization setup in
Quartus® Prime. Thus, options in the PDN tool can be used as a
22.214.171.124.7. VRM Impedance Section
Enter the VRM impedance values for the regulators. Use the pull-down menu to
enter data for VRM Resistance and VRM Inductance.
There are three ways to change the voltage regulator module (VRM) parameters.
Depending on what you select in the VRM Impedance
pull-down menu, you can:
and set your desired Rvrm and Lvrm values.
and get the suggested typical Rvrm and Lvrm values. This depends on the type of regulator
(for example, switching, linear, or filter) you have selected.
and Rvrm and Lvrm
For switching regulators, you can choose a specific
Enpirion® VRM (based on ordering code) directly in the
Enpirion® models in the VRM library
already include base required output capacitance for a base/default supported current.
You must obtain the base/default output capacitors from the
Enpirion® datasheet of the device you
to include into your PCB decoupling caps, if you select an
Figure 8. VRM Model
The R1 and L1 effect occurs at approximately 1 kHz to 50 kHz, which represents the
regulator normal RL circuit without the closed loop.
The R2 and L2 effect occurs at 50 kHz to 300 kHz and represents the effect of the closed
The Cout branch effect occurs between 300 kHz and 1 MHz.
The PDN tool can help you select the appropriate
Enpirion® VRM module to use for each power
supply in your system.
126.96.36.199.8. BGA Via Section
The BGA Via table shows the L and R
values per via. You can set the tool to Calculate,
Custom, Default, or Ignore. For a fully
customized workflow in which each rail group can have different settings, set the total
effective R and L values in the BGA Via section to
match your system.
If you set the BGA Via table to
Calculate or Ignore, the System_Decap tab uses the
same global settings for all rail groups.
If you set the BGA Via table to Default, the PDN tool calculates the R and L values similarly to the Calculate option, however, the tool also calculates the number
of power/ground via pairs based on the rails connected to the regulator group. You can input
the layer number in the tool. The layer number should match the target layer in Full Stackup. Then, BGA via R and L
calculated corresponding to the layer number.
Figure 9. Setting the Layer Number
188.8.131.52.9. Plane Section
In the Plane table, you can set the tool to Calculate, Custom, or Ignore. For a fully customized workflow in which each rail group can have different settings:
Select the Plane_Cap tab in the PDN tool 2.0.
Set the parameters to match your system, and notice that the Total planar capacitance and Total sheet resistance values are updated automatically.
In the System_Decap tab, select the Custom option for each group where a custom plane is required.
Enter the calculated Ctotal and Rtotal values into the Plane section of the System_Decap tab.
Setting the Plane table to Calculate or Ignore causes the System_Decap tab to use the same global settings for all rail groups.
184.108.40.206.10. Spreading Section
In the Spreading table, you can set the tool to one of the following options:
For a fully customized workflow in which each rail group can have different settings:
Select the Library tab in the PDN tool 2.0.
Set the parameters in the Spreading R and L table to match your system.
Examine the range of spreading R and L values to determine if you need a custom R and L. If a custom R and L is warranted, select Custom in the System_Decap tab and set the R and L values directly.
Setting the Spreading table to Low, Medium, High, or Ignore causes the System_Decap tab to use the same global settings for all rail groups.
220.127.116.11.11. Implementing Split Planes
Each group of power rails shares the same regulator. Therefore, separate power rail groups
have separate regulators. However, they might share the same power plane layer (but separate
power islands with different dimensions). Alternatively, each power rail group can be located
on a different power plane layer.
If the regulator groups share the same power plane, select the same Layer
Number under BGA Via in the
Figure 10. Set the Layer Number
Perform these steps in the Stackup tab:
Complete the Stackup Data table.
Click Import Geometries.
Figure 11. Complete the Stackup Data Table
Perform these steps in the Plane_Cap tab:
Specify the dimensions of the area allocated to each regulator group.
Change the import target from All to the group ID.
Click Import Plane R&C.
Figure 12. Import the Plane R&C
18.104.22.168.12. FEFFECTIVE Section
You can set Feffective to Calculate or Override.
Select the Calculate option to use the Intel-recommended cut off frequency based on package and die
22.214.171.124.13. Decoupling Section
You can set Decoupling to Manual or Auto. If you select the Auto option, any change you make to the system is automatically reflected in the decoupling solution. You can also view the impedance chart per rail group or VRM.
Selecting the Manual option allows you to:
Lock in calculated decoupling solutions from being further optimized by any changes made to the System_Decap tab.
Add or remove the number and type of decoupling capacitors in the Results Summary section. You can see its immediate impact on the impedance profile curve.
126.96.36.199.14. Results Summary Section
You can find the list of the number and type of capacitors used for each group, and the
summary of all the capacitors used. The values in each column indicate the number of
capacitors needed of each value for each rail.
The results section may show a very large number of capacitors required to
decouple some power rails. Changes in various worksheets that supply data to this worksheet
substantial effect on the capacitors required.
Figure 13. Results Summary Section of the System_Decap Tab
188.8.131.52.15. Recommended Flow for Deriving Decoupling for an FPGA System using the System_Decap Tab
To use the
System_Decap tab, perform the following steps:
Select the appropriate device family or device.
Set up the stack up information in the
The tool updates the power rail connection configuration to
the scheme recommended in the Pin Connection Guidelines.
Ensure that the
following default parameters match your system, and make the necessary changes
relativity of power
rails within the same power group
power group layer
number of power/ground
DC voltage supply for
Enter the projected
current consumption of each power rail.
Enter the PCB stackup information of your design in the
Stackup tab. This tab updates related data in the
Cap_Mount and the
X2Y_Mount tabs. The stackup information in this
tab is also used for the
System_Decap tab. Follow the instructions provided
at the beginning of the tab to fill in the content for this tab.
Figure 14. Stackup Tab
184.108.40.206.1. Stackup Data
The Stackup Data section is where you enter board dimension data and other
parameters, such as board stackup settings, power via, and dielectric material.
220.127.116.11.2. Full Stackup
This section lists the complete stackup of your board. You can modify
content in the section to better match your board design. The last column in
the section is the
PWR plane types. In a single rail analysis case,
assign the layer where the power rail is located as
target, and the ground layer that the power rail
refers to as
Table 4. Full Stackup Buttons
Populates the Full
Stackup section to the number of layers defined in the
Stackup Data section.
Updates geometry parameters in the
BGA_Via, Plane_Cap, Cap_Mount, and X2Y_Mount tabs using your input from the
Stackup Data section. The tool also checks that the PWR Planes column in the Full
Stackup section has only one target layer, and provides a warning for this error.
Proceed to System Decap
Opens the System_Decap tab.
BGA Via tab calculates the vertical via loop
inductance under the
BGA pin field.
Figure 15. BGA_Via TabThe values in the Unit column indicate a
unit value per one pair.
Enter the layout-specific information such as via drill diameters, via
length, via pitch, and the number of power/ground via pairs under the BGA in the
BGA Via Inductance table. The tool calculates the
effective via loop inductance and resistance value. You can save the change
made to the tab, restore the changes, or restore the tab back to the default
Plane Cap tab calculates the distributed plane
capacitance in microfarads (µF) that is developed between the power/ground
planes based on the parallel plate capacitor equation.
Figure 16. Plane_Cap Tab
Enter the design specific information such as plane dimensions, plane
configuration and the dielectric material used in the Planar
Capacitance table. The tool calculates a plane capacitance value. You
can save custom values, restore custom values, or restore the default settings.
The Import Plane R&C button inserts the data
for the planar capacitance into the regulator group data.
Cap Mount tab calculates the capacitor mounting
inductance seen by the decoupling capacitor.
Note: Power rails on different layers have different mounting inductances. For the best
results, run the PDN separately for each layer set.
Figure 17. Cap Mount Tab
The capacitor mounting calculation is based on the assumption that the
decoupling capacitor is a two-terminal device. The capacitor mounting calculation is
applicable to any two-terminal capacitor with the following footprints: 0201, 0402,
0603, 0805, and 1206. Enter all the information relevant to your layout, and the tool
provides a mounting inductance for a capacitor mounted on either the top or bottom layer
of the board. Depending on the layout, you can choose between VOE (Via on End) or VOS
(Via on Side) to achieve an accurate capacitor mounting inductance value. Generally,
VOS can have lower mounting inductance due to a smaller via pitch. Also, X2Y cap can be
considered as a solution for a space-limited design.
If you plan to use a footprint capacitor other than a regular
two-terminal capacitor or X2Y capacitor for decoupling, you can skip the
Cap Mount tab. In this case, you can directly
enter the capacitor parasitics and capacitor mounting inductance in the
Library tab (under the
Custom field in the Decoupling
Cap section of the library). As with the other tabs, you can save
the changes made to the tab, restore the changes, or restore the tab back to
the default settings.
You must pay special attention to the via lengths for the capacitors. Via inductance
comprises a substantial portion of the PDN impedance.
X2Y Mount tab calculates the capacitor mounting
inductance seen by the X2Y decoupling capacitor.
Figure 18. X2Y_Mount Tab
Enter all the information relevant to your layout in the
X2Y CAP Mounting Inductance table. The tool then
provides a mounting inductance for an X2Y capacitor mounted on either the top
or bottom layer of the board. You can save the changes made to the tab, restore
the changes, or restore the tab back to the default settings.
Library tab stores all the device parameters that
are referred to in the other tabs.
Figure 19. Library Tab
You can change each of the default values listed in the respective
sections to meet the specific needs of your design.
18.104.22.168.1. Two-Terminal Decoupling Capacitors
The decoupling capacitors section contains the default ESR and ESL
values for the various two-terminal capacitors in the following footprints:
You also have the option to either modify the default values or enter
your own commonly used custom values in the
Custom field. If you are using a capacitor with a
footprint that is not available in the tool, you must use the
Custom field to enter the capacitor parasitics and
the corresponding mounting inductance.
The decoupling capacitors section also provides the option for
capacitors (such as User1 through User4). You can define the ESR and ESL parasitics for
the various footprints and enter the corresponding capacitor value in the System_Decap tab. Choose the corresponding footprint
when defining the capacitor values.
22.214.171.124.2. Bulk Capacitors
The bulk capacitors section contains the commonly used capacitor values
for decoupling the power supply at mid and low frequencies. You can change the
default values to reflect the parameters specific to the design.
126.96.36.199.3. X2Y Decoupling Capacitors
The X2Y decoupling capacitors section contains the default ESR and ESL
values for the various X2Y capacitors in the 0603, 0805, 1206, and 1210
footprints. You also can replace the default ESR and ESL values with your own
commonly used custom values.
188.8.131.52.4. BGA Via and Plane Capacitance
This section allows you to directly enter the values for effective via
loop inductance under the BGA and plane capacitance during the pre-layout phase
when no design-specific information is available.
If you have access to design-specific information, you can ignore this
section and enter the design-specific information in the
Plane Cap and
BGA Via tabs that calculate the plane capacitance
and the BGA via parasitics, respectively.
184.108.40.206.5. VRM Library
The VRM section lists the default values for both the linear and
switcher regulators. In the
Custom field, you can change the VRM parasitics
listed under the linear/switcher rows or add the custom parasitics for the VRM
relevant to the design.
220.127.116.11.6. Spreading R and L Parasitics
This library provides various options for the default effective
spreading inductance values that the decoupling capacitors see with respect to
the FPGA. These values are based on the quality of the PDN design. You can
Low value of effective spreading inductance if you
have optimally designed your PDN Network. Optimum PDN design involves
implementing the following design rules:
PCB stackup that provides a wide solid
power/ground sandwich for a given supply with a thin dielectric between the planes.
The thickness of the dielectric material between the power/ground pair directly
influences the amount of spreading/loop inductance that a decoupling cap can see
with respect to the FPGA.
Placing the capacitors
closer to the FPGA from an electrical standpoint.
Minimizing via perforations
in the power/ground sandwich in the current path from the decoupling caps to
the FPGA device.
Due to layout and design constraints, the PDN design may not be optimal.
In this case, you can choose either a
High value of spreading R and L. You can also
change the default values or use the
Custom field listed in the library specific to the
18.104.22.168.7. Dielectric Material Library
This library lists the dielectric constant values for the various
commonly used dielectric materials. These values are used in the plane
capacitance calculations listed under the
Plane_Cap tab. You can change the values listed in
If you change the default values listed in the various sections in the
Library tab, you can save the changes by clicking
Save Custom. You can restore the default library
Restore Default located at the top right-hand
corner of the
Library page. You can also restore the saved
custom library by clicking
22.214.171.124.8. User Set FEFFECTIVE
You must decouple to an FEFFECTIVE higher than what
is calculated for the power rails of some device families. In this case, you must set the
FEFFECTIVE option to Override in the System_Decap tab. The PDN
tool 2.0 then uses the FEFFECTIVE value entered here.
In the Enlarged_Graph tab, you can view
the enlarged Z-profile plot. The PDN tool 2.0 switches to this tab when you
the Z-profile plot in the System_Decap tab. You
can go back to the System_Decap tab when you
click the Return button.
Figure 20. Enlarged_Graph Tab
1.2.3. Design PCB Decoupling Using the PDN Tool 2.0
PCB decoupling keeps the PDN ZEFF smaller than ZTARGET with the properly chosen PCB capacitor combination up to the
frequency where the capacitance on the package and die take over the PDN decoupling. This
procedure uses the PDN tool 2.0 in different power rail configurations and provides design
examples using the
Stratix® 10 device PDN tool.
126.96.36.199. Pre-Layout Instructions
The PDN tool 2.0 provides an accurate estimate of the number and types of
capacitors needed to design a robust power delivery network, regardless of where you are
in the design phase. However, the accuracy of the results depends highly on
inputs for the various parameters.
If you have finalized the board stackup and have access to board
database and layout information, you can proceed through the tabs and enter the
required information to arrive at an accurate decoupling scheme.
In the pre-layout phase of the design cycle when you do not have specific
information about the board stack-up and board layout, you can follow
these instructions to explore the solution space when finalizing key design
parameters such as stackup, plane size, capacitor count, capacitor orientation,
and so on.
In the pre-layout phase, ignore the
Plane Cap and
Cap Mount tabs and go directly to the
Library tab when you do not have the layout
information. If available, enter the values shown below in the
Library tab. To use the default values, go
directly to the
System_Decap tab to begin the analysis.
Figure 21. Library Tab FieldsThe callouts correspond to the fields in which you must enter
Enter the ESR, ESL, and Lmnt
values for the capacitors listed in the
Enter the effective BGA via
parasitics for the power supply being decoupled in the BGA Via & Plane Cap field.
Enter the plane capacitance
seen by the power/ground plane pair on the board for the power supply in the
BGA Via & Plane Cap field.
Enter the VRM parasitics, if
available, in the
Custom row of the
Enter the effective
spreading inductance seen by the decoupling capacitors in the
Custom row of the
Spreading R and L field.
188.8.131.52. Deriving Decoupling in a Single-Rail Scenario
A power supply connects to only one power rail on the FPGA device in a
single-rail scenario. The PDN noise is created by the dynamic current change of
the single rail. You determine ZTARGET and FEFFECTIVE
based on the parameters related to the selected rail only.
The PDN tool 2.0 provides two ways to derive a decoupling network. You can
set up the tool with the information needed and let the tool derive the PDN
decoupling for your system. You can also manually enter the information and
derive decoupling. To derive the desired capacitor combination:
Select the device/power rail to work with.
parameter settings for the PDN components.
Enter the electric
parameters to set ZTARGET and FEFFECTIVE.
You need to have a good estimate of the parameters entered
to derive the proper decoupling guidelines (ZTARGET and
FEFFECTIVE). Although you need to determine those guidelines based
on the worst-case scenario, pessimistic settings result in hard-to-achieve
guidelines and over design of your PCB decoupling.
Derive the PCB
You must adjust the number and value of the PCB capacitors in the Decoupling Capacitor (Mid/High Frequency)
and Decoupling Capacitor (Bulk)
fields to keep the plotted ZEFF below ZTARGET until FEFFECTIVE. You can derive the decoupling for the selected power rail
manually. You can also select the Auto
Decouple button and let the PDN tool 2.0 automatically
determine a decoupling solution. If you are not able to find a capacitor
combination that meets your design goal, you can try to change the
parameters at 2. For example, you can reduce the BGA via inductance
used in the Calculate option by
reducing the BGA via length in the BGA_VIA tab and using the low option for plane spreading. These changes reduce
parasitic inductance and make it easier to achieve your decoupling goal. To
achieve the low spreading setting, you must place the mid to high frequency
PCB capacitors close to the FPGA device. You also must minimize the
dielectric thickness between the power and ground plane. Refer to Troubleshooting ZEFF
if the ZEFF is too high or the number of
capacitors for decoupling becomes too high.
If you are not able to meet the ZTARGET requirement with
the changes above, the PDN in your design may have reached its physical
limitation under the electrical parameters you entered for ZTARGET
and FEFFECTIVE. You should re-examine these parameters to check if
they are overly pessimistic.
Figure 22. Enlarged Plot of ZEFFThis sample impedance plot is for a 1SG280LU_F50 VCC power rail. Assume that
the minimum voltage supply is 0.8 V, Idynamic is 50
A, dynamic current change is 30% of Idynamic, and the
maximum allowable die noise tolerance is 5% of supply voltage. The VCC rail has
169 power BGA vias. The length of BGA via is assumed to be 20 mil.
The PDN tool 2.0 calculated that ZTARGET is 0.0027 Ω
and FEFFECTIVE is 13.58 MHz. The figure above shows one
of the capacitor combinations that you can select to meet the design goal. As shown
in the plot, ZEFF remains under ZTARGET up to FEFFECTIVE. There are many
combinations, but the ideal solution is to minimize the quantity and the type of
capacitors needed to achieve a flat impedance profile below the ZTARGET.
184.108.40.206. Deriving Decoupling in the Power-Sharing Scenarios
It is a common practice that several power rails in the FPGA device share the same
power supply. For example, you can connect VCCPT, VCCA_PLL, and VCCA_FPLL rails that
require the same supply voltage to the same PCB power plane. This can be required by the
design, such as in the memory interface case. This can also come from the need to reduce
bill of materials (BOM) cost. You can use the System_Decap tab to facilitate the decoupling design for the power
When deriving decoupling capacitors for multiple FPGAs sharing the same
power plane, each FPGA should be analyzed separately using the PDN tool 2.0. For
each FPGA design, combine the required power rails as described above and
analyze the decoupling scheme as if the FPGA was the only device on the power
rail, taking note of how the current is divided across the devices.
High frequency decoupling capacitors are meant to provide the current
needed for AC transitions, and must be placed in a close proximity to the FPGA
power pins. Thus, the PDN tool 2.0 should be used to derive the required decoupling
capacitors for the unique power requirements for each FPGA on the board.
The power regulators must be able to supply the total combined current
requirements for each load on the supply, but the decoupling capacitor
selections should be analyzed on a single FPGA basis.
1.2.4. Troubleshooting ZEFF
When the decoupling mode is set to Auto, this may result in a
ZEFF value that is too high. This can happen when the PCB parameters you entered
result in an inefficient PDN, and the current to be decoupled by the PCB are unrealistically
With difficult PCB and current parameters, auto decoupling continues to add decoupling
capacitors until it determines they have little effect. This results in hundreds of
capacitors. You can achieve decoupling schemes with similar performance manually using far
220.127.116.11. Strategies for Correcting a High ZEFF
As well as decoupling manually, you can reduce the decoupling
burden by accurately estimating your current requirements and making your PCB more efficient.
You may be able to achieve reduced PCB current requirements in the following ways:
Estimating realistic current requirements in the Early Power Estimator (EPE).
Entering realistic toggle rate figures for the logic in the EPE.
Unrealistically high toggle rates dramatically increases dynamic current requirements.
Entering realistic logic requirements in the EPE.
Entering realistic clock frequencies in the EPE.
Quartus® Prime software
simulation entry for accurate current requirement estimation.
Considering Root Sum Squared (RSS) averaging for shared power supply
rails. Refer to the Introduction tab of the PDN tool
for more information
You can make the PCB more efficient in the following ways:
Increasing inter-plane capacitance of your Power (PWR) and Ground (GND) plane pair by
reducing their dielectric thickness.
Increasing inter-plane capacitance of your PWR and GND plane pair by increasing their
Reducing loop inductance from the PWR and GND plane pair to the FPGA. You can do this by
moving them closer to the surface of the PCB where the FPGA is mounted.
Reducing loop inductance from the high frequency decoupling capacitors to the PWR and GND
plane pair. You can do this by placing them on the surface of the PCB that is closest to the
Using Via On Side (VOS) instead of Via On End (VOE) capacitor mounting topologies to help
at high frequencies.
Using ultra-low Effective Series Inductance (ESL) mounting capacitors to help at high
frequencies, for example, X2Y package style.
Using ultra-low Effective Series Resistance (ESR) bulk capacitors to help at low
Considering larger vias with less ESL.
Realistic tool entry can make decoupling easier to achieve. The following factors affect the
calculation of ZTARGET:
An increase in dynamic current reduces ZTARGET and makes decoupling difficult
to achieve. See the guidelines above.
Enter realistic noise or ripple figures into the PDN tool. Use the noise
figure listed in the device and rail specific table in the Introduction tab of the PDN Tool. Unrealistic ripple requirements reduce
ZTARGET and make decoupling difficult.
Enter realistic transient % figures into the PDN tool. Use the transient % figure listed
in the device and rail specific table in the Introduction tab of the
PDN Tool. Unrealistic transient % requirements reduce ZTARGET and make decoupling
The PDN Tool 2.0 includes the following new pessimism removal features to make decoupling the
large core current manageable:
Core clock frequency
Current ramp up period
Note: These features are available only for the core rail.
1.3. PDN Tool Setup and Result Optimization
Note: If your PDN tool does not update automatically, ensure that you set the Microsoft Excel*
Calculation option as follows: Formulas > Calculation Options > Automatic.
1.3.1. Setting Up a PCB Stackup
This step-by-step guide helps you get optimal PDN decoupling estimation using
Intel's PDN tool. This example is common for all product families
supported by the PDN tool.
18.104.22.168. Selecting Your Device
Click the System_Decap tab.
Select your Device and click Yes
in the confirmation dialog box.
22.214.171.124. Inputting Stackup Data
Click the Stackup tab.
Input your stackup values for the following parameters:
Number of Layers
BGA Via pitch
Select a dielectric material from the Dielectric
Material drop-down menu.
Note: If you are using a custom dielectric material, skip this step and proceed
to the Using a Custom Dielectric Material section.
Click Construct Stackup, then click
Yes in the Construct Stackup
confirmation dialog box.
The Full Stackup section updates based on your
Enter the Thickness values for each layer in the
Full Stackup table, then click Import
The PDN tool automatically calculates the target impedance (ZTARGET) based
on the recommended Dynamic Current Change% and Noise
Figure 25. Rail Group SummaryBoxes shaded in light blue are drop-down menus with different options to select. Core
Clock Frequency and Current Ramp Up Period options vary depending on your design.
With these options enabled, the ZTARGET curve relaxes from certain frequencies
based on the inputs.
Figure 26. Flat versus Curved ZTARGET
126.96.36.199. VRM Impedance
The PDN tool has default Library R and L models for VRM
If a VRM model is available from the vendor, you can select the Custom option to
replace the default values by directly overriding the new values.
Figure 27. VRM Impedance
Note: The single R and L assumption in the tool is for 1-phase single VRM. For multi-phase VRM
usage, the simplest method for rough estimation is to divide the default numbers by the number
of phases. For example, if the default values for a single switcher and four-phase VRM are R =
1 mΩ and L = 20 nH, then you can estimate the final values as R = 0.25 mΩ and L = 5 nH. Make
note of how many phases of VRM you use in each PDN design. The tool may recommend bulk cap
solutions that are significantly different.
188.8.131.52. BGA Via
Once you select a power rail, the PDN tool automatically updates the number of
Power/GND Via pairs. Every device has a different number.
The tool automatically calculates the parasitics when you enter your expected
layer number in the Layer Number field by overriding for
power rail location in the stackup.
Figure 28. BGA ViaThe Layer Number field also has the
Ignore, Custom, and
Note: You can use the BGA_Via tab as a stand-alone tool for custom via parasitic
184.108.40.206. Calculating Plane
Based on your layer location assumption, the tool automatically calculates the plane R
Click the Stackup tab.
Enter your expected plane length and width values in the Plane
Length and Plane Width fields,
This is the best method for estimating if the layout design is already in
progress (see the following figure).
Figure 29. Plane Size EstimationThe tool only measures the plane size from the VRM to the FPGA.
Select which layers you want to use as target (power) and reference (ground,
two layers maximum) in the Full Stackup table.
Click Import Geometries on the left side of the
Full Stackup table.
Click the Plane_Cap tab.
The tool automatically updates the plane parasitics.
Change the regulator group number in the Import the calculated Plane
R & Plane C to regulator Group field, then click
Import Plane R&C.
Figure 30. Plane_Cap Table
Click the System_Decap tab and verify that the tool has updated the
Note: The PDN tool does not support the multi-layered design for a single power.
However, you can repeat 1
through 6 for each power
layer, keeping the estimated parasitic numbers of each and combining
capacitances of each power for final capacitance and calculating resistances
of each power in parallel to get the final resistance. For example, if both
layers nine and 10 of roughly the same size plane have one power rail, the
tool calculates the parasitics based on one power and one reference layer in
the Full Stackup table as shown in the figure below.
Then, the final capacitance can be 0.0016 x 2 = 0.0032 µF and the final
resistance can be 0.001 / 2 = 0.0005 Ω.
Figure 31. Plane Parasitics
220.127.116.11. Plane Spreading Parasitics
For plane spreading parasitics, you can use pre-defined
Library values, Custom, or
The default spreading setting is Low. Depending on the location of
your decaps, you may also select Medium or
Figure 32. Spreading
18.104.22.168. FEFFECTIVE and Decoupling Result Summary
The following figure shows final decoupling recommendations based on the inputs in the tool.
However, even though ZPDN meets the ZTARGET up to FEFFECTIVE,
the number of capacitors, 301, are not suitable for the real design. Refer to the
Optimization Method section for details about optimizing your results.
Figure 33. Decoupling Results Summary
1.3.3. Optimizing in Pre-Layout
22.214.171.124. Checking the Capacitor Model
Capacitors, especially bulk caps, can be replaced with capacitors with
Click the Library
If there are RLC models with lower parasitics, replace the
existing capacitors with them.
Replace bulky Tantal Polymer capacitors with
Multi-layered Ceramic Capacitor (MLCC) caps with similar
electrical/thermal characteristics. 100uF, 220uF, and 330uF caps with
much lower ESR and ESL are available.
Using the decap library effectively in the PDN
in a more accurate estimation.
Use User and Custom
options for additional capacitors.
Figure 34. Library of Capacitors
126.96.36.199. Optimizing the Decap Count
Since the tool is a code-based
spreadsheet, it keeps adding up the number of decoupling capacitors until ZPDN satisfies ZTARGET up to FEFFECTIVE. The PDN tool has a 301ea maximum decap
Change the Decoupling
mode from Auto to Manual.
There can be a ±5% variation on ZEFF impedance when doing
decoupling caps optimization. This impedance variation can relate to
Observing the impedance plot carefully, optimize the number of each
Figure 36. Manual Decoupling Results Summary - Post-Optimization, Round 1After optimizing manually, 301ea decaps are dramatically reduced to
124ea while maintaining a similar ZPDN
profile (the red curve) under the same ZTARGET.
Figure 37. Manual Decoupling Results Summary - Post-Optimization Results, Round 1A small amount of violation at different frequencies can reduce the number of decaps.
Before and after results are shown below.
1.3.4. Further Optimizing for Better Accuracy
While the two methods described in Optimizing in Pre-Layout are
mainly used in the pre-layout stage for a rough estimation of the decoupling solution, the
method described here shows how to get a more accurate and optimized estimation.
the Capacitor Model updates the decoupling capacitor library with the actual
models used and Optimizing the Decap Count controls the
number of decaps in manual mode, this method shows how to exclude Spreading R and L from
the estimation process. As shown in the figure below, there is no mechanical restriction
in populating decaps on the other side of the FPGA and red boxes indicate 70ea of 0402in
decaps which can be directly placed; the majority of the total 124ea decaps can be
populated right under BGAs. Thus, the spreading option might be negligible in this
Figure 38. Populating Decaps on the Other Side of the FPGA
Change Feffective option from
Calculate to Override.
Check whether or not the number remains the same.
If the number changes, write the recommended FEFFECTIVE, 10.18 MHz in the example below, into the
Figure 39. FEFFECTIVE
Change the Spreading
option from Low to Ignore.
Once the spreading option is ignored, the entire ZPDN
little, which means more margin.
Figure 40. Ignoring Spreading
Repeat the manual optimization for each cap as shown in Optimizing the Decap Count.
After the optimization process, only 48ea of 0402in capacitors
(circled with a red box below) are estimated while the total allowable number of
0402in capacitors is 70ea. Also, the rest of the larger capacitors (circled with
a blue box below) in this example can be populated in the BGA area. Final
results are shown below. The total number of capacitors was decreased down to
77ea from the max limit of 301ea, including bulk capacitors, through round 1 and
2 of the optimization process.
Note: The PDN
tool result already includes the bulk capacitor solution for VRM. However,
Intel recommends checking with the VRM vendor about the required output
capacitance to check if the PDN tool estimation can cover the requirement.
Enpirion® models in the VRM
library already include the required output capacitance. For the required
capacitor combination, please refer to the datasheet of each VRM
The following results show the correlation between the PDN tool and the post-layout system
PDN impedance profile (lower right figure) for one of Intel's development kit boards. In the
post-layout analysis, the simple VRM model from the PDN tool was used. Since the PDN tool is
already considering PKG and die parasitics, both results are well correlated.
Note: The PDN tool does not display the on-die capacitance in the result graph. Die capacitance
is utilized for determining FEFFECTIVE.
Figure 42. PDN Tool
1.4. Device-Specific PDN Tool 2.0 Known Issues and Their Solutions
Table 5. Device-Specific PDN Tool 2.0 Known Issues and Their Solutions
Why does the PDN tool suggest 0 bulk
decoupling capacitors with low-current power supply