Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide
ID
683293
Date
8/24/2021
Public
1.2.2.1.1. Device Selection Section
1.2.2.1.2. Power Rail Data and Configuration Section
1.2.2.1.3. Meeting Target Impedance when Entering 0 A into the PDN Tool
1.2.2.1.4. Dealing with Multiple Shared Power Supply Pin Types
1.2.2.1.5. VRM Data Section
1.2.2.1.6. Rail Group Summary Section
1.2.2.1.7. VRM Impedance Section
1.2.2.1.8. BGA Via Section
1.2.2.1.9. Plane Section
1.2.2.1.10. Spreading Section
1.2.2.1.11. Implementing Split Planes
1.2.2.1.12. FEFFECTIVE Section
1.2.2.1.13. Decoupling Section
1.2.2.1.14. Results Summary Section
1.2.2.1.15. Recommended Flow for Deriving Decoupling for an FPGA System using the System_Decap Tab
1.2.2.7.6. Spreading R and L Parasitics
This library provides various options for the default effective spreading inductance values that the decoupling capacitors see with respect to the FPGA. These values are based on the quality of the PDN design. You can choose a Low value of effective spreading inductance if you have optimally designed your PDN Network. Optimum PDN design involves implementing the following design rules:
- PCB stackup that provides a wide solid power/ground sandwich for a given supply with a thin dielectric between the planes. The thickness of the dielectric material between the power/ground pair directly influences the amount of spreading/loop inductance that a decoupling cap can see with respect to the FPGA.
- Placing the capacitors closer to the FPGA from an electrical standpoint.
- Minimizing via perforations in the power/ground sandwich in the current path from the decoupling caps to the FPGA device.
Due to layout and design constraints, the PDN design may not be optimal. In this case, you can choose either a Medium or High value of spreading R and L. You can also change the default values or use the Custom field listed in the library specific to the design.