Backplane Ethernet 10GBASE-KR PHY Intel® FPGA IP Core

The Backplane Ethernet 10GBASE-KR PHY Intel® FPGA Intellectual Property (IP) core is a transceiver PHY that allows you to instantiate both the hard standard physical coding sublayer (PCS) and the higher performance hard 10G PCS, and hard physical medium attachment (PMA) for a single Backplane Ethernet channel. It implements the functionality described in the IEEE 802.3ap-2007 standard. Because each instance of the 10GBASE-KR PHY IP core supports a single channel, you can create multichannel designs by instantiating more than one instance of the core.

Read the Intel® Stratix® 10 10GBASE-KR PHY IP Core user guide ›

Read the Intel® Arria® 10 Transceiver PHY user guide ›

Read the Stratix® V device handbook ›

Backplane Ethernet 10GBASE-KR PHY Intel® FPGA IP Core

IP Quality Metrics

Basics

Year IP was first released

2012

First version of Intel Quartus Prime Software supported

16.1

Ordering Code

IP-10GBASEKRPHY

Status

Production

Deliverables

Customer deliverables include the following:

    Design file (encrypted source code or post-synthesis netlist)

    Simulation model for ModelSim*-Intel FPGA Edition

    Timing and/or layout constraints

    Documentation with revision control

    Readme file

Y

Any additional customer deliverables provided with IP

 

Parameterization GUI allowing end user to configure IP

Y

IP core is enabled for Intel FPGA IP Evaluation Mode Support

Y

Source language

Verilog

Testbench language

 

Software drivers provided

N

Driver OS Support

 

Implementation

User interface

GMII and SGMII

IP-XACT metadata

N

Verification

Simulators supported

Mentor Graphics*, Synopsys*, Cadence*

Hardware validated

Intel Arria 10, Intel Stratix 10

Industry-standard compliance testing performed

N

If Yes, which test(s)?

 

If Yes, on which Intel FPGA device(s)?

 

If Yes, date performed

 

If No, is it planned?

Y

Interoperability

IP has undergone interoperability testing

N

If yes, on which Intel FPGA device(s)

 

Interoperability reports available

N