Video and Vision Processing Suite
The Intel® FPGA Video and Vision Processing Suite is a collection of next-generation Intel® FPGA intellectual property (IP) functions that you can use to facilitate the development of custom video and image processing designs. These Intel® FPGA IP functions are suitable for use in a wide variety of image processing and display applications, such as studio broadcast, video conferencing, AV networking, medical imaging, industrial inspections and robotics, smart city/retail and consumer.
Video and Vision Processing Suite Intel® FPGA IP User Guide ›
Video and Vision Processing Suite
The Video and Vision Processing Suite features IPs that range from simple building block functions such as clocked video and genlock suite, color space conversion, and mixer to sophisticated processing functions that can implement programmable scaling, arbitrary non-linear distortion correction, 3D look-up table, adaptive tone mapping and many more.
- All the Video and Vision Processing IPs use Intel® FPGA streaming video data interfaces for video I/O, based on the industry standard AXI4-Stream protocol.
- You can mix and match video and image processing IPs with your own proprietary IP.
- Utilizing Intel® Agilex™ FPGA architecture – the Video and Vision Processing Suite is capable of processing 8K video at 60fps with four pixels in parallel at 600MHz.
- Support for processing flexibility of 1-8 pixels in parallel.
- Support for 1-4 color symbols per pixel and RGB and YCbCr 444, 422 and 420 color spaces.
- Data precision of 8-16 bits per symbol.
- Video fields with 1-16384 pixels in both height and width.
Avalon memory-mapped agent interfaces for runtime control and Avalon memory-mapped host interface for external memory usage allow push-button conversion in Intel Platform Designer to industry standard AXI4-S or AXI4-Stream memory mapped interfaces if required.
- You can use Video and Vision Processing IP to build a custom video and image processing signal chain using the Platform Designer, as well as to automatically integrate embedded processors and peripherals and generate arbitration logic.
Features
Video and Image Processing Suite Intel FPGA IP Functions
Intel FPGA IP Function |
Description |
|---|---|
The Clocked Video Interface IPs convert clocked video formats (such as BT656, BT1120, and DVI) to AXI4-Streaming video; and vice versa. |
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Remaps pixel data and video timing information from Intel FPGA streaming full-raster protocol to clocked video format. |
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Remaps pixel data and video timing information from clocked video format to Intel FPGA streaming full-raster protocol. |
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Provides a seamless conversion between Intel FPGA streaming full-raster and Intel FPGA streaming video lite protocols. |
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Broadcasts a single input video bus (in multiple formats) to multiple destinations. |
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Routes discrete signals around an FPGA design under software control. An M inputs to N outputs data crosspoint for single bit signals. |
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Multi-channel genlock strobe extractor and router. This IP allows passing genlock timing signals to internal or external FPGA multi-rate video clock generators, to facilitate video input and output clock genlock and/or frame synchronization, based on video timing markers derived from video connectivity IP. |
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Generates real-time video timing signals according to Full-Raster or Clocked Video standards. |
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Generates a video stream that contains a test pattern. |
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Crops an active area from a video stream and discards the remainder. |
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Provides an efficient solution for video color space and dynamic range conversions, chroma-keying, and the creation of artistic effects. |
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Applies geometric corrections and arbitrary non-linear distortions to a real-time video stream. |
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Corrects poorly exposed images and video to reveal invisible details. |
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Resizes input video stream to produce output of a different height and or width. |
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Implements a 3x3, 5x5, or 7x7 finite impulse response (FIR) filter on an image data stream to smooth or sharpen images. |
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Switch |
Allows video streams to be switched in real time. |
Allows you to overlay video fields from multiple inputs on each other, either with or without alpha blending (transparency). Mixer is used for implementing text overlay and picture-in-picture mixing. |
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Converts between the different chroma sampling formats available in the YCbCr color space, for example from 4:2:2 to 4:4:4 or 4:2:2 to 4:2:0. |
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Converts video data between color spaces such as RGB to YCbCr. |
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Convert image data between a variety of different color spaces such as RGB to YCrCb. |
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Buffers video frames into external RAM. This IP supports double or triple-buffering with a range of options for frame dropping and repeating. |
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Converts between three interface protocols: Avalon streaming video, Intel FPGA streaming video lite variant and Intel FPGA streaming video full variant. |
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Allows multiple pixels to be transmitted in a single clock cycle (beat). Converts from one value of pixels in parallel at the input interface to a higher or lower number of pixels in parallel at the output interface. |
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Compares each color plane in the input video stream to upper and lower guard bands values. It replaces the pixel value falling outside of the guard bands by the respective guard band values. |
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Provides a FIFO buffer storage solution with input and output interfaces compliant to the Intel FPGA streaming video protocol. |
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Converts interlaced video formats to progressive video format using a deinterlacing algorithm. Currently only supports "bob" algorithm ("weave," low-angle edge detection, 3:2 cadence detection and motion adaptive to be added in future). |
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Removes and repairs the non-ideal sequences and error cases present in the incoming data stream to produce an output stream that complies with the implicit ideal use model. |
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Color Plane Sequencer |
Changes how color plane samples are transmitted across the Intel FPGA video streaming protocol. This function can be used to split and join video streams, giving control over the routing of color plane samples. |
Gamma Corrector |
Allows video streams to be corrected for the physical properties of display devices. |
Interlacer |
Converts progressive video to interlaced video by dropping half the lines of incoming progressive frames. |
IP Quality Metrics
Basics |
|
|---|---|
Year IP was first released |
2021 |
Latest version of Intel® Quartus® software supported? |
Yes |
Status |
Production |
Deliverables |
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Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Timing and/or layout constraints Testbench or design example Documentation with revision control |
Yes Yes Yes |
Any additional customer deliverables provided with IP |
None |
Parameterization GUI allowing end user to configure IP |
Yes |
IP is enabled for Intel FPGA IP Evaluation Mode Support |
Yes |
Source language |
System Verilog |
Testbench language |
System Verilog |
Software drivers provided |
Yes |
Driver operating system (OS) support |
Bare metal |
Implementation |
|
User interface |
Clocked Video (into relevant IPs), Avalon Streaming Video, Intel FPGA Streaming Full Faster, Intel FPGA Streaming Video, Intel Avalon Memory-Mapped |
IP-XACT metadata |
No |
Verification |
|
Simulators supported |
VCS, VCS MX, Active-HDL, Riviera-PRO, Xcelium, Questa-Intel FPGA Edition, Questa |
Hardware validated |
Intel® Arria® 10 GX |
Industry standard compliance testing performed |
No |
If Yes, which test(s)? |
N/A |
If Yes, on which Intel FPGA device(s)? |
N/A |
If Yes, date performed |
N/A |
If No, is it planned? |
N/A |
Interoperability |
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IP has undergone interoperability testing |
Yes |
If yes, on which Intel FPGA device(s) |
Intel® Cyclone® 10, Intel® Arria® 10, Intel® Stratix® 10, Intel Agilex |
Interoperability reports available |
N/A |