3D LUT Intel® FPGA IP
3D look-up tables (LUTs) Intel FPGA IP provide an efficient solution for video colorspace and dynamic range conversions, chroma-keying, and the creation of artistic effects.
3D LUT Intel FPGA IP Product Brief ›
Video and Vision Processing Suite Intel® FPGA IP User Guide ›
3D LUT Intel® FPGA IP
3D LUT Intel FPGA IP provides an efficient solution for video color-space conversions and conversion between nonlinear gamuts. This IP also enables many other artistic and cinematic effects, such as sepia tone, monochrome, color changes, vintage, vivid color, cool/warm film and the ability to create chroma-keys to separate foreground from a colored background. The 3D LUT IP employs Tetrahedral interpolation. The 3D LUT IP uses the most significant bits (MSBs) of the 3-color component inputs to retrieve data values from the contents of the LUT (in FPGA memory), and the least significant bits (LSBs) to interpolate the final output value. The interpolation processes and memory methods used in Intel’s 3D LUT IP use a lower number of gates and memory than competing solutions, enabling practical 3D LUT implementations using an FPGA for a more cost-effective solution. The low resource count and industry standard interfaces such as AXI4-Streaming and AXI4-Lite allow the IP to be easily integrated into your Intel FPGA design.
3D LUT on Intel® Arria® 10 SX FPGA Demo
Watch the video to see an in-house technical expert demonstrate the capabilities of the 3D LUT Intel® FPGA IP.
UDX Warp TMO 3D LUT (WT3) Intel® Arria® 10 FPGA IP SoC Example Design
The design example used in the video is based on the Intel Arria 10 SX FPGA UHD HDMI 2.0 Video Format Conversion design with a simplified video pipeline and web-based GUI controls to operate and program showcased IPs. It demonstrates the operation of Warp, TMO and 3DLUT Intel FPGA IPs. To download this design example, log into your intel.com account.
Features
- Support for 17³, 33³ and 65³ LUTs
- Support 3 and 4 output channels from the LUT (Alpha /key channel)
- High quality tetrahedral interpolation
- Independently set input/output pixel depth
- Independently set LUT precision
- Dynamic update of table values with optional double buffering to enable clean synchronous switching to a new LUT
- Includes ‘.cube’ file format conversion utility
- Support for 8, 10, 12 and 16 bit per color component
- Support up to 4 pixels in parallel (PIP) per clock processing
- Low subframe latency (21 clock cycles)
- Support resolutions up to 4K at 60 fps on Intel® C10/A10/S10 FPGAs and up to 8K at 60 fps on Intel® Agilex™ 7 FPGAs
- Low FPGA resource utilization
- AXI4-Stream video I/O interface
- AXI4-Stream ↔ Avalon® streaming interface Protocol Converters
- Avalon memory mapped CPU control and memory interfaces
IP Quality Metrics
Basics |
|
|---|---|
Year IP was first released |
2021 |
Latest version of Intel® Quartus® design software supported |
Yes |
Status |
Production |
Deliverables |
|
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Timing and/or layout constraints User guide |
Yes |
Any additional customer deliverables provided with IP |
Testbench and design example |
Parameterization GUI allowing end user to configure IP |
Yes |
IP core is enabled for Intel FPGA IP Evaluation Mode Support |
Yes |
Source language |
Verilog |
Testbench language |
Verilog |
Software drivers provided |
Yes |
Driver OS Support |
Bare metal |
Implementation |
|
User interface |
Intel FPGA Streaming Video Protocol, Intel Avalon Memory-Mapped |
IP-XACT metadata |
No |
Verification |
|
Simulators supported |
VCS, VCS MX, Active-HDL, Riviera-PRO, Xcelium, Questa-Intel FPGA Edition, Questa |
Hardware validated |
Intel® Arria® 10 GX |
Industry-standard compliance testing performed |
No |
If Yes, which test(s)? |
N/A |
If Yes, on which Intel FPGA device(s)? |
N/A |
If Yes, date performed |
N/A |
If No, is it planned? |
N/A |
Interoperability |
|
IP has undergone interoperability testing |
Yes |
If yes, on which Intel FPGA device(s) |
Intel® Cyclone® 10, Intel® Arria® 10, Intel® Straitix® 10, Intel Agilex |
Interoperability reports available |
No |
UDX 3D LUT Intel FPGA IP Design Example on Intel® Arria® 10 GX FPGA
This design example is based on the Intel® Arria® 10 GX FPGA UHD HDMI 2.0 Video Format Conversion design with a simplified video pipeline and additional controls to operate and program the 3D LUT. It demonstrates how the IP maps a video stream's color space to another using interpolated values from a lookup table.
Need Help with Your Design?
The Intel® FPGA design services team have developed a pool of expertise and a wealth of intellectual property (IP) to solve customer design challenges in the areas of intelligent video and vision processing. Our experienced and skilled designers are motivated to meet your design needs with the most efficient and innovative solutions, using our library of highly optimized and proven IP. We cover a wide variety of applications ranging from high-volume consumer electronics to mid-volume specialist design in markets including—but not limited to—medical imaging, ProAV, industrial, military, and broadcast.
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