3D LUT Intel® FPGA IP

3D look-up tables (LUTs) Intel FPGA IP provide an efficient solution for video colorspace and dynamic range conversions, chroma-keying, and the creation of artistic effects.

3D LUT Intel® FPGA IP

3D LUT Intel FPGA IP

3D LUT Intel FPGA IP provides an efficient solution for video color-space conversions and conversion between nonlinear gamuts. This IP also enables many other artistic and cinematic effects, such as sepia tone, monochrome, color changes, vintage, vivid color, cool/warm film and the ability to create chroma-keys to separate foreground from a colored background. The 3D LUT IP employs Tetrahedral interpolation. The 3D LUT IP uses the most significant bits (MSBs) of the 3-color component inputs to retrieve data values from the contents of the LUT (in FPGA memory), and the least significant bits (LSBs) to interpolate the final output value. The interpolation processes and memory methods used in Intel’s 3D LUT IP use a lower number of gates and memory than competing solutions, enabling practical 3D LUT implementations using an FPGA for a more cost-effective solution. The low resource count and industry standard interfaces such as AXI4-Streaming and AXI4-Lite allow the IP to be easily integrated into your Intel FPGA design.

Features

  • Support for 17³, 33³ and 65³ LUTs
  • Support 3 and 4 output channels from the LUT (Alpha /key channel)
  • High quality tetrahedral interpolation
  • Independently set input/output pixel depth
  • Independently set LUT precision
  • Dynamic update of table values with optional double buffering to enable clean synchronous switching to a new LUT
  • Includes ‘.cube’ file format conversion utility
  • Support for 8, 10, 12 and 16 bit per color component
  • Support up to 4 pixels in parallel (PIP) per clock processing
  • Low subframe latency (21 clock cycles)
  • Support resolutions up to 4K at 60 fps on Intel® C10/A10/S10 FPGAs and up to 8K at 60 fps on Intel® Agilex™ FPGAs
  • Low FPGA resource utilization
  • AXI4-Stream video I/O interface
  • AXI4-Stream ↔ Avalon® streaming interface Protocol Converters
  • Avalon memory mapped CPU control and memory interfaces

IP Quality Metrics

Basics

Year IP was first released

2021

Latest version of Intel® Quartus® design software supported

21.3

Status

Production

Deliverables

Customer deliverables include the following:

    Design file (encrypted source code or post-synthesis netlist)

    Timing and/or layout constraints

    User guide

Yes

Any additional customer deliverables provided with IP

Testbench and design example

Parameterization GUI allowing end user to configure IP

Yes

IP core is enabled for Intel FPGA IP Evaluation Mode Support

Yes

Source language

Verilog

Testbench language

Verilog

Software drivers provided

Yes

Driver OS Support

Bare metal

Implementation

User interface

Intel FPGA Streaming Video Protocol, Intel Avalon Memory-Mapped

IP-XACT metadata

No

Verification

Simulators supported

VCS, VCS MX, Active-HDL, Riviera-PRO, Xcelium, Questa-Intel FPGA Edition, Questa

Hardware validated

Intel® Arria® 10 GX

Industry-standard compliance testing performed

No

If Yes, which test(s)?

N/A

If Yes, on which Intel FPGA device(s)?

N/A

If Yes, date performed

N/A

If No, is it planned?

N/A

Interoperability

IP has undergone interoperability testing

Yes

If yes, on which Intel FPGA device(s)

Intel® Cyclone® 10, Intel® Arria® 10, Intel® Straitix® 10, Intel Agilex

Interoperability reports available

No
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