Warp Intel® FPGA IP
The Warp Intel® FPGA IP is a highly optimized IP core for applying geometric corrections and arbitrary non-linear distortions to a real-time video stream.
Warp Intel® FPGA IP Product Brief ›
Video and Vision Processing Suite Intel® FPGA IP User Guide ›
Warp Intel® FPGA IP
Overview
The Warp Intel FPGA IP is a highly optimized core for applying geometric corrections and arbitrary non-linear distortions to a real-time video stream of up to 3,840 x 2,160 pixels and up to 60 frames per second. Maximum image quality is achieved through per-pixel filtering with bi-cubic interpolation on full color resolution 4:4:4 video data at up to 10-bits per color plane. The Warp Intel FPGA IP is delivered with a set of software components including a software driver that configures and controls all of the necessary parameters of the IP, a warp data generator, and an example warp mesh generator. The software can be deployed on a Nios® II processor-based system or SoC (recommended).
Features
- Arbitrary warp transforms and rotations
- Highly optimized external memory interface
- 0.5x to 2x local scaling
- High quality per-pixel bi-cubic interpolation
- Coefficient sets available for highest filter quality
- Full data buffering to allow input and output to operate on independent clock domains
- Support for 10 bit per color component
- Support up to 2 pixels in parallel per clock processing
- Low latency
- Support resolutions up to 3840 × 2160 at 60 fps and future support for up to 8K at 60 fps
- Low FPGA resource utilization
- AXI4-Stream video I/O interface
- AXI4-Stream ↔ Avalon® stream interface Protocol Converters
- Avalon memory mapped CPU control and memory interfaces
IP Quality Metrics
Basics |
|
|---|---|
Year IP was first released |
2021 |
Latest version of Intel® Quartus® design software supported |
21.3 |
Status |
Production |
Deliverables |
|
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Timing and/or layout constraints User guide |
Yes |
Any additional customer deliverables provided with IP |
Testbench and design example |
Parameterization GUI allowing end user to configure IP |
Yes |
IP core is enabled for Intel FPGA IP Evaluation Mode Support |
Yes |
Source language |
Verilog |
Testbench language |
Verilog |
Software drivers provided |
Yes |
Driver OS Support |
Bare metal |
Implementation |
|
User interface |
Intel FPGA Streaming Video Protocol, Intel Avalon Memory-Mapped |
IP-XACT metadata |
No |
Verification |
|
Simulators supported |
VCS, VCS MX, Active-HDL, Riviera-PRO, Xcelium, Questa-Intel® FPGA Edition, Questa |
Hardware validated |
Intel® Arria® 10 GX |
Industry-standard compliance testing performed |
No |
If Yes, which test(s)? |
N/A |
If Yes, on which Intel FPGA device(s)? |
N/A |
If Yes, date performed |
N/A |
If No, is it planned? |
N/A |
Interoperability |
|
IP has undergone interoperability testing |
Yes |
If yes, on which Intel FPGA device(s) |
Intel® Cyclone® 10, Intel® Arria® 10, Intel® Stratix® 10, Intel® Agilex™ |
Interoperability reports available |
No |
Design Example
Based on the Intel® Arria® 10 UHD HDMI 2.0 Video Format Conversion design with a simplified video pipeline and additional controls to operate and program the IP.
Need Help with Your Design?
The Intel® FPGA design services team have developed a pool of expertise and a wealth of intellectual property (IP) to solve customer design challenges in the areas of intelligent video and vision processing. Our experienced and skilled designers are motivated to meet your design needs with the most efficient and innovative solutions, using our library of highly optimized and proven IP. We cover a wide variety of applications ranging from high-volume consumer electronics to mid-volume specialist design in markets including—but not limited to—medical imaging, ProAV, industrial, military, and broadcast.
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