Altera® AXI4 Bus Functional Model User Guides

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ID 838773
Date 5/19/2025
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Altera® AXI4 Memory-Mapped BFM User Guide 2. Altera® AXI4 Streaming BFM User Guide 3. Document Revision History of Altera® AXI4 Bus Functional Model User Guides A. API Translation: Mentor* VIP to Altera® AXI4 Memory-Mapped BFM
1. Altera® AXI4 Memory-Mapped BFM User Guide x
1.1. Altera® AXI4 Memory-Mapped BFM Overview 1.2. Altera® AXI4 Memory-Mapped BFM Architecture 1.3. Altera® AXI4 Memory-Mapped BFM Configuration and Interfaces 1.4. Using the Altera® AXI4 Memory-Mapped BFMs 1.5. Altera® AXI4 Memory-Mapped BFM API 1.6. Altera® AXI4 Memory-Mapped Assertions
1.1. Altera® AXI4 Memory-Mapped BFM Overview x
1.1.1. Altera® AXI4 Memory-Mapped Specification Support 1.1.2. Altera® AXI4 Memory-Mapped BFM Components 1.1.3. Altera® AXI4 Memory-Mapped Supported Features 1.1.4. Altera® AXI4 Memory-Mapped BFM SystemVerilog Packages 1.1.5. Altera® AXI4 Memory-Mapped BFM Supported Flows 1.1.6. Altera® AXI4 Memory-Mapped BFM Supported Simulators
1.2. Altera® AXI4 Memory-Mapped BFM Architecture x
1.2.1. Altera® AXI4 Memory-Mapped Manager BFM Architecture 1.2.2. Altera® AXI4 Memory-Mapped Subordinate BFM Architecture 1.2.3. Altera® AXI4 Memory-Mapped Monitor BFM Architecture 1.2.4. Altera® AXI4 Memory-Mapped BFM Transaction Class
1.2.4. Altera® AXI4 Memory-Mapped BFM Transaction Class x
1.2.4.1. Altera® AXI4 Transaction Information
1.3. Altera® AXI4 Memory-Mapped BFM Configuration and Interfaces x
1.3.1. Altera® AXI4 Memory-Mapped Manager BFM Configuration 1.3.2. Altera® AXI4 Memory-Mapped Manager BFM Interface 1.3.3. Altera® AXI4 Memory-Mapped Subordinate BFM Configuration 1.3.4. Altera® AXI4 Memory-Mapped Subordinate BFM Interface 1.3.5. Altera® AXI4-Lite Memory-Mapped Manager BFM Configuration 1.3.6. Altera® AXI4-Lite Memory-Mapped Manager BFM Interface 1.3.7. Altera® AXI4-Lite Memory-Mapped Subordinate BFM Configuration 1.3.8. Altera® AXI4-Lite Memory-Mapped Subordinate BFM Interface 1.3.9. Altera® AXI4 Memory-Mapped Inline Monitor Configuration 1.3.10. Altera® AXI4 Inline Monitor Interface
1.4. Using the Altera® AXI4 Memory-Mapped BFMs x
1.4.1. Using the Altera® AXI4 Memory-Mapped Manager BFM Flow 1.4.2. Using the Altera® AXI4 Memory-Mapped Subordinate BFM Flow 1.4.3. Using the Altera® AXI4 Memory-Mapped Monitor BFM Flow 1.4.4. Altera® AXI4 Memory-Mapped Manager RTL Implementation Example 1.4.5. Altera® AXI4 Memory-Mapped Manager Platform Designer BFM Implementation Example
1.5. Altera® AXI4 Memory-Mapped BFM API x
1.5.1. Altera® AXI4 Memory-Mapped BFM Configuration API 1.5.2. Altera® AXI4 Memory-Mapped BFM Reset API 1.5.3. Altera® AXI4 Memory-Mapped Manager Transaction Creation API 1.5.4. Altera® AXI4 Memory-Mapped Subordinate Transaction Creation API 1.5.5. Altera® AXI4 Memory-Mapped Transaction Configuration API 1.5.6. Altera® AXI4 Memory-Mapped BFM Transaction Execution API 1.5.7. Altera® AXI4 Memory-Mapped Host Memory API
2. Altera® AXI4 Streaming BFM User Guide x
2.1. Altera® AXI4 Streaming BFM Overview 2.2. Altera® AXI4 Streaming BFM Architecture 2.3. Altera® AXI4 Streaming BFM Configuration and Interfaces 2.4. Using the Altera® AXI4 Streaming BFMs 2.5. Altera® AXI4 Streaming BFM Packages, Classes, Interfaces, and Modules
2.1. Altera® AXI4 Streaming BFM Overview x
2.1.1. AXI4 Protocol Specification Support 2.1.2. Altera® AXI4 Streaming BFM Components 2.1.3. AXI4 Streaming Supported Features 2.1.4. Altera® AXI4 Streaming BFM SystemVerilog Packages 2.1.5. Altera® AXI4 Streaming BFM Supported Flows 2.1.6. Altera® AXI4 Streaming BFM Supported Simulators
2.2. Altera® AXI4 Streaming BFM Architecture x
2.2.1. Altera® AXI4 Streaming BFM Data Organization 2.2.2. AXI4 Streaming Data Transfer 2.2.3. Altera® AXI4 Streaming Transmitter BFM 2.2.4. Altera® AXI4 Streaming Receiver BFM
2.2.1. Altera® AXI4 Streaming BFM Data Organization x
2.2.1.1. Altera® AXI4 Streaming BFM Beats 2.2.1.2. Altera® AXI4 Streaming BFM Transfers 2.2.1.3. Altera® AXI4 Streaming BFM Packets
2.3. Altera® AXI4 Streaming BFM Configuration and Interfaces x
2.3.1. Altera® AXI4 Streaming Transmitter BFM Configuration 2.3.2. Altera® AXI4 Streaming Transmitter BFM Interfaces 2.3.3. Altera® AXI4 Streaming Receiver BFM Configuration 2.3.4. Altera® AXI4 Streaming Receiver BFM Interface
2.4. Using the Altera® AXI4 Streaming BFMs x
2.4.1. Using the Transmitter BFM Flow 2.4.2. Using the Receiver BFM Flow 2.4.3. Altera® AXI4 Streaming BFM Tools 2.4.4. Altera® AXI4 Streaming BFM RTL Example 2.4.5. Altera® AXI4 Streaming BFM Platform Designer Example
2.4.3. Altera® AXI4 Streaming BFM Tools x
2.4.3.1. Number Formatting 2.4.3.2. Transfer Printing 2.4.3.3. Transfer Comparison
2.5. Altera® AXI4 Streaming BFM Packages, Classes, Interfaces, and Modules x
2.5.1. Altera® AXI4 Streaming Common BFM Packages, Classes, Interfaces, and Modules 2.5.2. Altera® AXI4 Streaming Transmitter BFM Packages, Classes, and Modules 2.5.3. Altera® AXI4 Streaming Receiver BFM Packages, Classes, and Modules
2.5.1. Altera® AXI4 Streaming Common BFM Packages, Classes, Interfaces, and Modules x
2.5.1.1. Package axi4_stream_bfm_types_pkg 2.5.1.2. Package axi4_stream_bytes_class_pkg 2.5.1.3. Package axi4_stream_transfer_class_pkg 2.5.1.4. Package axi4_stream_packet_class_pkg
2.5.1.1. Package axi4_stream_bfm_types_pkg x
2.5.1.1.1. Typedefs 2.5.1.1.2. Utility Function num_formatter 2.5.1.1.3. Interface axi4_stream_if 2.5.1.1.4. AXI4 Streaming Interface Modports 2.5.1.1.5. Protocol-Checking Assertions
2.5.1.2. Package axi4_stream_bytes_class_pkg x
2.5.1.2.1. Class Axi4StreamBytes 2.5.1.2.2. Data Members in Axi4StreamBytes Class 2.5.1.2.3. Methods in Axi4StreamBytes Class 2.5.1.2.4. Class Axi4StreamBytesData 2.5.1.2.5. Methods in Axi4StreamBytesData Class 2.5.1.2.6. Class Axi4StreamBytesPosition 2.5.1.2.7. Methods in Axi4StreamBytesPosition Class 2.5.1.2.8. Class Axi4StreamBytesNull 2.5.1.2.9. Methods in Axi4StreamBytesNull Class 2.5.1.2.10. Class Axi4StreamBytesDataError 2.5.1.2.11. Data Members in Axi4StreamBytesDataError Class 2.5.1.2.12. Methods in Class Axi4StreamBytesDataError 2.5.1.2.13. Class Axi4StreamBytesPositionError 2.5.1.2.14. Data Members in Class Axi4StreamBytesPositionError 2.5.1.2.15. Methods in Class Axi4StreamBytesPositionError 2.5.1.2.16. Class Axi4StreamBytesNullError 2.5.1.2.17. Data Members in Class Axi4StreamBytesNullError 2.5.1.2.18. Methods in Class Axi4StreamBytesNullError
2.5.1.3. Package axi4_stream_transfer_class_pkg x
2.5.1.3.1. Class Axi4StreamTransfer 2.5.1.3.2. Data Members in Class Axi4StreamTransfer 2.5.1.3.3. Methods in Class Axi4StreamTransfer
2.5.1.4. Package axi4_stream_packet_class_pkg x
2.5.1.4.1. Class Axi4StreamPacket 2.5.1.4.2. Data Members in Class Axi4StreamPacket 2.5.1.4.3. Methods in Class Axi4StreamPacket
2.5.2. Altera® AXI4 Streaming Transmitter BFM Packages, Classes, and Modules x
2.5.2.1. Package axi4_stream_bfm_transmit_pkg.sv
2.5.2.1. Package axi4_stream_bfm_transmit_pkg.sv x
2.5.2.1.1. Class TransmitBFM 2.5.2.1.2. Module axi4_stream_bfm_transmit_top 2.5.2.1.3. Method Prototypes in Class TransmitBFM
2.5.3. Altera® AXI4 Streaming Receiver BFM Packages, Classes, and Modules x
2.5.3.1. Package axi4_stream_bfm_receive_pkg.sv
2.5.3.1. Package axi4_stream_bfm_receive_pkg.sv x
2.5.3.1.1. Class ReceiveBFM 2.5.3.1.2. Module axi4_stream_bfm_receive_top 2.5.3.1.3. Method Prototypes in Class ReceiveBFM
Answers to Top FAQs
1. Altera® AXI4 Memory-Mapped BFM User Guide
2. Altera® AXI4 Streaming BFM User Guide
3. Document Revision History of Altera® AXI4 Bus Functional Model User Guides
A. API Translation: Mentor* VIP to Altera® AXI4 Memory-Mapped BFM

2.2.3. Altera® AXI4 Streaming Transmitter BFM

AXI4 streaming communication occurs when one block sends a stream of data, and then another block receives the sent data. The following describes the transmitter side of the transfer that initiates the data transfer.

Altera AXI4 Streaming BFM Transmitter Block Diagram shows the top-down functionality of the Altera® AXI4 Streaming Transmitter BFM. The top level axi4_stream_bfm_transmit_top module of the transmitter is in the altera_lnsim library.

Figure 12. Altera AXI4 Streaming Transmitter BFM Block Diagram

Data to be sent via the transmitter is placed in the transmitter’s send_input_packet_queue input packet queue on the left side of the block diagram. The queue is a SystemVerilog queue of type Axi4StreamPacket[$]. You can place BFM packet objects into the send_input_packet_queue using the put_packet_for_transmit BFM method. Refer to examples in AXI4 Streaming Platform Designer Example and AXI4 Streaming BFM RTL Example.

The transfer objects in the packet container are taken out of send_input_packet_queue in the order entered and placed in the axis_send block transaction delay queue, tdq. tdq handles the delay and gap timing for the transfer, while holding the data ready for transmission at the appropriate time. When the time arrives for data transmission, the data is stored in the data_queue byte queue. data_queue immediately presents the data and the appropriate beat-specific data fields for transmission. The transmitter’s axis.tvalid and axis.tlast output control signals are driven by the Send State Machine using the receiver’s axis.tready signal as an input. The AXI4 streaming interface is then directly driven from these final logic blocks of axis_send for reception by the downstream receiver.

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