Altera® AXI4 Bus Functional Model User Guides

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ID 838773
Date 5/19/2025
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Altera® AXI4 Memory-Mapped BFM User Guide 2. Altera® AXI4 Streaming BFM User Guide 3. Document Revision History of Altera® AXI4 Bus Functional Model User Guides A. API Translation: Mentor* VIP to Altera® AXI4 Memory-Mapped BFM
1. Altera® AXI4 Memory-Mapped BFM User Guide x
1.1. Altera® AXI4 Memory-Mapped BFM Overview 1.2. Altera® AXI4 Memory-Mapped BFM Architecture 1.3. Altera® AXI4 Memory-Mapped BFM Configuration and Interfaces 1.4. Using the Altera® AXI4 Memory-Mapped BFMs 1.5. Altera® AXI4 Memory-Mapped BFM API 1.6. Altera® AXI4 Memory-Mapped Assertions
1.1. Altera® AXI4 Memory-Mapped BFM Overview x
1.1.1. Altera® AXI4 Memory-Mapped Specification Support 1.1.2. Altera® AXI4 Memory-Mapped BFM Components 1.1.3. Altera® AXI4 Memory-Mapped Supported Features 1.1.4. Altera® AXI4 Memory-Mapped BFM SystemVerilog Packages 1.1.5. Altera® AXI4 Memory-Mapped BFM Supported Flows 1.1.6. Altera® AXI4 Memory-Mapped BFM Supported Simulators
1.2. Altera® AXI4 Memory-Mapped BFM Architecture x
1.2.1. Altera® AXI4 Memory-Mapped Manager BFM Architecture 1.2.2. Altera® AXI4 Memory-Mapped Subordinate BFM Architecture 1.2.3. Altera® AXI4 Memory-Mapped Monitor BFM Architecture 1.2.4. Altera® AXI4 Memory-Mapped BFM Transaction Class
1.2.4. Altera® AXI4 Memory-Mapped BFM Transaction Class x
1.2.4.1. Altera® AXI4 Transaction Information
1.3. Altera® AXI4 Memory-Mapped BFM Configuration and Interfaces x
1.3.1. Altera® AXI4 Memory-Mapped Manager BFM Configuration 1.3.2. Altera® AXI4 Memory-Mapped Manager BFM Interface 1.3.3. Altera® AXI4 Memory-Mapped Subordinate BFM Configuration 1.3.4. Altera® AXI4 Memory-Mapped Subordinate BFM Interface 1.3.5. Altera® AXI4-Lite Memory-Mapped Manager BFM Configuration 1.3.6. Altera® AXI4-Lite Memory-Mapped Manager BFM Interface 1.3.7. Altera® AXI4-Lite Memory-Mapped Subordinate BFM Configuration 1.3.8. Altera® AXI4-Lite Memory-Mapped Subordinate BFM Interface 1.3.9. Altera® AXI4 Memory-Mapped Inline Monitor Configuration 1.3.10. Altera® AXI4 Inline Monitor Interface
1.4. Using the Altera® AXI4 Memory-Mapped BFMs x
1.4.1. Using the Altera® AXI4 Memory-Mapped Manager BFM Flow 1.4.2. Using the Altera® AXI4 Memory-Mapped Subordinate BFM Flow 1.4.3. Using the Altera® AXI4 Memory-Mapped Monitor BFM Flow 1.4.4. Altera® AXI4 Memory-Mapped Manager RTL Implementation Example 1.4.5. Altera® AXI4 Memory-Mapped Manager Platform Designer BFM Implementation Example
1.5. Altera® AXI4 Memory-Mapped BFM API x
1.5.1. Altera® AXI4 Memory-Mapped BFM Configuration API 1.5.2. Altera® AXI4 Memory-Mapped BFM Reset API 1.5.3. Altera® AXI4 Memory-Mapped Manager Transaction Creation API 1.5.4. Altera® AXI4 Memory-Mapped Subordinate Transaction Creation API 1.5.5. Altera® AXI4 Memory-Mapped Transaction Configuration API 1.5.6. Altera® AXI4 Memory-Mapped BFM Transaction Execution API 1.5.7. Altera® AXI4 Memory-Mapped Host Memory API
2. Altera® AXI4 Streaming BFM User Guide x
2.1. Altera® AXI4 Streaming BFM Overview 2.2. Altera® AXI4 Streaming BFM Architecture 2.3. Altera® AXI4 Streaming BFM Configuration and Interfaces 2.4. Using the Altera® AXI4 Streaming BFMs 2.5. Altera® AXI4 Streaming BFM Packages, Classes, Interfaces, and Modules
2.1. Altera® AXI4 Streaming BFM Overview x
2.1.1. AXI4 Protocol Specification Support 2.1.2. Altera® AXI4 Streaming BFM Components 2.1.3. AXI4 Streaming Supported Features 2.1.4. Altera® AXI4 Streaming BFM SystemVerilog Packages 2.1.5. Altera® AXI4 Streaming BFM Supported Flows 2.1.6. Altera® AXI4 Streaming BFM Supported Simulators
2.2. Altera® AXI4 Streaming BFM Architecture x
2.2.1. Altera® AXI4 Streaming BFM Data Organization 2.2.2. AXI4 Streaming Data Transfer 2.2.3. Altera® AXI4 Streaming Transmitter BFM 2.2.4. Altera® AXI4 Streaming Receiver BFM
2.2.1. Altera® AXI4 Streaming BFM Data Organization x
2.2.1.1. Altera® AXI4 Streaming BFM Beats 2.2.1.2. Altera® AXI4 Streaming BFM Transfers 2.2.1.3. Altera® AXI4 Streaming BFM Packets
2.3. Altera® AXI4 Streaming BFM Configuration and Interfaces x
2.3.1. Altera® AXI4 Streaming Transmitter BFM Configuration 2.3.2. Altera® AXI4 Streaming Transmitter BFM Interfaces 2.3.3. Altera® AXI4 Streaming Receiver BFM Configuration 2.3.4. Altera® AXI4 Streaming Receiver BFM Interface
2.4. Using the Altera® AXI4 Streaming BFMs x
2.4.1. Using the Transmitter BFM Flow 2.4.2. Using the Receiver BFM Flow 2.4.3. Altera® AXI4 Streaming BFM Tools 2.4.4. Altera® AXI4 Streaming BFM RTL Example 2.4.5. Altera® AXI4 Streaming BFM Platform Designer Example
2.4.3. Altera® AXI4 Streaming BFM Tools x
2.4.3.1. Number Formatting 2.4.3.2. Transfer Printing 2.4.3.3. Transfer Comparison
2.5. Altera® AXI4 Streaming BFM Packages, Classes, Interfaces, and Modules x
2.5.1. Altera® AXI4 Streaming Common BFM Packages, Classes, Interfaces, and Modules 2.5.2. Altera® AXI4 Streaming Transmitter BFM Packages, Classes, and Modules 2.5.3. Altera® AXI4 Streaming Receiver BFM Packages, Classes, and Modules
2.5.1. Altera® AXI4 Streaming Common BFM Packages, Classes, Interfaces, and Modules x
2.5.1.1. Package axi4_stream_bfm_types_pkg 2.5.1.2. Package axi4_stream_bytes_class_pkg 2.5.1.3. Package axi4_stream_transfer_class_pkg 2.5.1.4. Package axi4_stream_packet_class_pkg
2.5.1.1. Package axi4_stream_bfm_types_pkg x
2.5.1.1.1. Typedefs 2.5.1.1.2. Utility Function num_formatter 2.5.1.1.3. Interface axi4_stream_if 2.5.1.1.4. AXI4 Streaming Interface Modports 2.5.1.1.5. Protocol-Checking Assertions
2.5.1.2. Package axi4_stream_bytes_class_pkg x
2.5.1.2.1. Class Axi4StreamBytes 2.5.1.2.2. Data Members in Axi4StreamBytes Class 2.5.1.2.3. Methods in Axi4StreamBytes Class 2.5.1.2.4. Class Axi4StreamBytesData 2.5.1.2.5. Methods in Axi4StreamBytesData Class 2.5.1.2.6. Class Axi4StreamBytesPosition 2.5.1.2.7. Methods in Axi4StreamBytesPosition Class 2.5.1.2.8. Class Axi4StreamBytesNull 2.5.1.2.9. Methods in Axi4StreamBytesNull Class 2.5.1.2.10. Class Axi4StreamBytesDataError 2.5.1.2.11. Data Members in Axi4StreamBytesDataError Class 2.5.1.2.12. Methods in Class Axi4StreamBytesDataError 2.5.1.2.13. Class Axi4StreamBytesPositionError 2.5.1.2.14. Data Members in Class Axi4StreamBytesPositionError 2.5.1.2.15. Methods in Class Axi4StreamBytesPositionError 2.5.1.2.16. Class Axi4StreamBytesNullError 2.5.1.2.17. Data Members in Class Axi4StreamBytesNullError 2.5.1.2.18. Methods in Class Axi4StreamBytesNullError
2.5.1.3. Package axi4_stream_transfer_class_pkg x
2.5.1.3.1. Class Axi4StreamTransfer 2.5.1.3.2. Data Members in Class Axi4StreamTransfer 2.5.1.3.3. Methods in Class Axi4StreamTransfer
2.5.1.4. Package axi4_stream_packet_class_pkg x
2.5.1.4.1. Class Axi4StreamPacket 2.5.1.4.2. Data Members in Class Axi4StreamPacket 2.5.1.4.3. Methods in Class Axi4StreamPacket
2.5.2. Altera® AXI4 Streaming Transmitter BFM Packages, Classes, and Modules x
2.5.2.1. Package axi4_stream_bfm_transmit_pkg.sv
2.5.2.1. Package axi4_stream_bfm_transmit_pkg.sv x
2.5.2.1.1. Class TransmitBFM 2.5.2.1.2. Module axi4_stream_bfm_transmit_top 2.5.2.1.3. Method Prototypes in Class TransmitBFM
2.5.3. Altera® AXI4 Streaming Receiver BFM Packages, Classes, and Modules x
2.5.3.1. Package axi4_stream_bfm_receive_pkg.sv
2.5.3.1. Package axi4_stream_bfm_receive_pkg.sv x
2.5.3.1.1. Class ReceiveBFM 2.5.3.1.2. Module axi4_stream_bfm_receive_top 2.5.3.1.3. Method Prototypes in Class ReceiveBFM
Answers to Top FAQs
1. Altera® AXI4 Memory-Mapped BFM User Guide
2. Altera® AXI4 Streaming BFM User Guide
3. Document Revision History of Altera® AXI4 Bus Functional Model User Guides
A. API Translation: Mentor* VIP to Altera® AXI4 Memory-Mapped BFM

1.6. Altera® AXI4 Memory-Mapped Assertions

Table 22.  AXI4 Assertions
AXI4 Assertion Description
AXI4_AWADDR_BOUNDARY A burst must not cross a 4kbyte boundary. AMBA AXI and ACE Protocol Specification, section A3.4.1.
AXI4_AWADDR_WRAP_ALIGN For a wrapping burst, the start address must be aligned to the size of each transfer. AMBA AXI and ACE Protocol Specification section A3.4.1.
AXI4_AWBURST When AWVALID is high, a value of 2'b11 on AWBURST is reserved. AMBA AXI and ACE Protocol Specification table A3-3.
AXI4_AWCACHE When AWVALID is high, a reserved value on AWCACHE is not allowed. AMBA AXI and ACE Protocol Specification table A4-5.
AXI4_ARCACHE When AWVALID is high, a reserved value on ARCACHE is not allowed. AMBA AXI and ACE Protocol Specification table A4-5.
AXI4_AWLEN_WRAP For a wrapping burst, the length of the burst must be 2, 4, 8 or 16 transfers. AMBA AXI and ACE Protocol Specification section A3.4.1.
AXI4_AWSIZE The size of any transfer must not exceed the data bus width of either agent in the transaction. AMBA AXI and ACE Protocol Specification section A3.4.1.
AXI4_AWVALID_RESET The earliest point after reset that a manager is permitted to begin driving ARVALID, AWVALID, or WVALID HIGH is at a rising ACLK edge after ARESETn is HIGH. AMBA AXI and ACE Protocol Specification Figure A3-1.
AXI4_AWADDR_STABLE AWADDR must remain stable when AWVALID is asserted and AWREADY low. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_AWBURST_STABLE AWBURST must remain stable when AWVALID is asserted and AWREADY low. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_AWCACHE_STABLE AWCACHE must remain stable when AWVALID is asserted and AWREADY low. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_AWID_STABLE AWID must remain stable when AWVALID is asserted and AWREADY low. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_AWLEN_STABLE AWLEN must remain stable when AWVALID is asserted and AWREADY low. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_AWLOCK_STABLE AWLOCK must remain stable when AWVALID is asserted and AWREADY low. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_AWPROT_STABLE AWPROT must remain stable when AWVALID is asserted and AWREADY low. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_AWSIZE_STABLE AWSIZE must remain stable when AWVALID is asserted and AWREADY low. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_AWQOS_STABLE AWQOS must remain stable when AWVALID is asserted and AWREADY low. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_AWREGION_STABLE AWREGION must remain stable when ARVALID is asserted and AWREADY low. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_AWVALID_STABLE Once AWVALID is asserted, it must remain asserted until AWREADY is high. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_AWADDR_X When AWVALID is high, a value of X on AWADDR is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_AWBURST_X When AWVALID is high, a value of X on AWBURST is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_AWCACHE_X When AWVALID is high, a value of X on AWCACHE is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_AWID_X When AWVALID is high, a value of X on AWID is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_AWLEN_X When AWVALID is high, a value of X on AWLEN is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_AWLOCK_X When AWVALID is high, a value of X on AWLOCK is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_AWPROT_X When AWVALID is high, a value of X on AWPROT is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_AWSIZE_X When AWVALID is high, a value of X on AWSIZE is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_AWQOS_X When AWVALID is high, a value of X on AWQOS is not permitted. Spec: section A3.2.2.
AXI4_AWREGION_X When AWVALID is high, a value of X on AWREGION is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_AWVALID_X When not in reset, a value of X on AWVALID is not permitted. AMBA AXI and ACE Protocol Specification section A3.1.2.
AXI4_AWREADY_X When not in reset, a value of X on AWREADY is not permitted. AMBA AXI and ACE Protocol Specification section A3.1.2.
AXI4_WDATA_NUM The number of write data items must match AWLEN for the corresponding address. AMBA AXI and ACE Protocol Specification section A3.4.1.
AXI4_WSTRB Write strobes must only be asserted for the correct byte lanes as determined from start address, transfer size and beat number. AMBA AXI and ACE Protocol Specification section A3.4.3.
AXI4_WVALID_RESET The earliest point after reset that a manager is permitted to begin driving ARVALID, AWVALID, or WVALID HIGH is at a rising ACLK edge after ARESETn is HIGH. AMBA AXI and ACE Protocol Specification Figure A3-1.
AXI4_WDATA_STABLE WDATA must remain stable when WVALID is asserted and WREADY low. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_WLAST_STABLE WLAST must remain stable when WVALID is asserted and WREADY low. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_WSTRB_STABLE WSTRB must remain stable when WVALID is asserted and WREADY low. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_WVALID_STABLE Once WVALID is asserted, it must remain asserted until WREADY is high. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_WDATA_X When WVALID is high, a value of X on active byte lanes of WDATA is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_WLAST_X When WVALID is high, a value of X on WLAST is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_WSTRB_X When WVALID is high, a value of X on WSTRB is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_WVALID_X When not in reset, a value of X on WVALID is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_WREADY_X When not in reset, a value of X on WREADY is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_BRESP_WLAST A subordinate must only give a write response after the last write data item is transferred. AMBA AXI and ACE Protocol Specification section A3.3.1 and figure A3-7.
AXI4_BRESP_EXOKAY An EXOKAY write response can only be given to an exclusive write access. AMBA AXI and ACE Protocol Specification section A7.2.
AXI4_BVALID_RESET The earliest point after reset that a manager is permitted to begin driving ARVALID, AWVALID, or WVALID HIGH is at a rising ACLK edge after ARESETn is HIGH. AMBA AXI and ACE Protocol Specification Figure A3-1.
AXI4_BRESP_AW A subordinate must not give a write response before the write address. AMBA AXI and ACE Protocol Specification section A3.3.1 and figure A3-7.
AXI4_BID_STABLE BID must remain stable when BVALID is asserted and BREADY low. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_BRESP_STABLE BRESP must remain stable when BVALID is asserted and BREADY low. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_BVALID_STABLE Once BVALID is asserted, it must remain asserted until BREADY is high. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_BREADY_X When not in reset, a value of X on BREADY is not permitted. AMBA AXI and ACE Protocol Specification section A3.1.2.
AXI4_BID_X When BVALID is high, a value of X on BID is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_BRESP_X When BVALID is high, a value of X on BRESP is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_BVALID_X When not in reset, a value of X on BVALID is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_ARADDR_BOUNDARY A burst must not cross a 4kbyte boundary. AMBA AXI and ACE Protocol Specification section A3.4.1.
AXI4_ARADDR_WRAP_ALIGN For a wrapping burst, the start address must be aligned to the size of each transfer. AMBA AXI and ACE Protocol Specification section A3.4.1.
AXI4_ARBURST When ARVALID is high, a value of 2'b11 on ARBURST is not permitted. AMBA AXI and ACE Protocol Specification table A3-3.
AXI4_ARLEN_FIXED Transactions of burst type FIXED cannot have a length greater than 16 beats. AMBA AXI and ACE Protocol Specification section A3.4.1.
AXI4_AWLEN_FIXED Transactions of burst type FIXED cannot have a length greater than 16 beats. AMBA AXI and ACE Protocol Specification section A3.4.1.
AXI4_AWLEN_LOCK Exclusive access transactions cannot have a length greater than 16 beats. AMBA AXI and ACE Protocol Specification section A7.2.4.
AXI4_ARLEN_LOCK Exclusive access transactions cannot have a length greater than 16 beats. AMBA AXI and ACE Protocol Specification section A7.2.4.
AXI4_ARLEN_WRAP For a wrapping burst, the length of the burst must be 2, 4, 8 or 16 transfers. AMBA AXI and ACE Protocol Specification section A3.4.1.
AXI4_ARSIZE The size of any transfer must not exceed the data bus width of either agent in the transaction. AMBA AXI and ACE Protocol Specification section A3.4.1.
AXI4_ARVALID_RESET The earliest point after reset that a manager is permitted to begin driving ARVALID, AWVALID, or WVALID HIGH is at a rising ACLK edge after ARESETn is HIGH. AMBA AXI and ACE Protocol Specification Figure A3-1.
AXI4_ARADDR_STABLE ARADDR must remain stable when ARVALID is asserted and ARREADY low. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_ARBURST_STABLE ARBURST must remain stable when ARVALID is asserted and ARREADY low. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_ARCACHE_STABLE ARCACHE must remain stable when ARVALID is asserted and ARREADY low. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_ARID_STABLE ARID must remain stable when ARVALID is asserted and ARREADY low. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_ARLEN_STABLE ARLEN must remain stable when ARVALID is asserted and ARREADY low. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_ARLOCK_STABLE ARLOCK must remain stable when ARVALID is asserted and ARREADY low. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_ARPROT_STABLE ARPROT must remain stable when ARVALID is asserted and ARREADY low. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_ARSIZE_STABLE ARSIZE must remain stable when ARVALID is asserted and ARREADY low. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_ARQOS_STABLE ARQOS must remain stable when ARVALID is asserted and ARREADY low. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_ARREGION_STABLE ARREGION must remain stable when ARVALID is asserted and ARREADY low. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_ARVALID_STABLE Once ARVALID is asserted, it must remain asserted until ARREADY is high. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_ARADDR_X When ARVALID is high, a value of X on ARADDR is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_ARBURST_X When ARVALID is high, a value of X on ARBURST is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_ARCACHE_X When ARVALID is high, a value of X on ARCACHE is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_ARID_X When ARVALID is high, a value of X on ARID is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_ARLEN_X When ARVALID is high, a value of X on ARLEN is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_ARLOCK_X When ARVALID is high, a value of X on ARLOCK is not permitted. Spec: section A3.2.2.
AXI4_ARPROT_X When ARVALID is high, a value of X on ARPROT is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_ARSIZE_X When ARVALID is high, a value of X on ARSIZE is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_ARQOS_X When ARVALID is high, a value of X on ARQOS is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_ARREGION_X When ARVALID is high, a value of X on ARREGION is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_ARVALID_X When not in reset, a value of X on ARVALID is not permitted. AMBA AXI and ACE Protocol Specification section A3.1.2.
AXI4_ARREADY_X When not in reset, a value of X on ARREADY is not permitted. AMBA AXI and ACE Protocol Specification section A3.1.2.
AXI4_RDATA_NUM The number of read data items must match the corresponding ARLEN. AMBA AXI and ACE Protocol Specification section A3.4.1.
AXI4_RID A subordinate can only give read data with an ID to match an outstanding read transaction. Spec: section A5.3.1.
AXI4_RRESP_EXOKAY An EXOKAY read response can only be given to an exclusive read access. AMBA AXI and ACE Protocol Specification section A7.2.3.
AXI4_RVALID_RESET The earliest point after reset that a manager is permitted to begin driving ARVALID, AWVALID, or WVALID HIGH is at a rising ACLK edge after ARESETn is high. AMBA AXI and ACE Protocol Specification Figure A3-1.
AXI4_RDATA_STABLE RDATA must remain stable when RVALID is asserted and RREADY low. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_RID_STABLE RID must remain stable when RVALID is asserted and RREADY low. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_RLAST_STABLE RLAST must remain stable when RVALID is asserted and RREADY low. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_RRESP_STABLE RRESP must remain stable when RVALID is asserted and RREADY low. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_RVALID_STABLE Once RVALID is asserted, it must remain asserted until RREADY is high. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_RDATA_X When RVALID is high, a value of X on RDATA valid byte lanes is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_RREADY_X When not in reset, a value of X on RREADY is not permitted. AMBA AXI and ACE Protocol Specification section A3.1.2.
AXI4_RID_X When RVALID is high, a value of X on RID is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_RLAST_X When RVALID is high, a value of X on RLAST is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_RRESP_X When RVALID is high, a value of X on RRESP is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_RVALID_X When not in reset, a value of X on RVALID is not permitted. AMBA AXI and ACE Protocol Specification section A3.1.2.
AXI4_EXCL_ALIGN The address of an exclusive access must be aligned to the total number of bytes in the transaction. AMBA AXI and ACE Protocol Specification section A7.2.4.
AXI4_EXCL_LEN The number of bytes to be transferred in an exclusive access burst must be a power of 2. AMBA AXI and ACE Protocol Specification section A7.2.4.
AXI4_EXCL_MAX The maximum number of bytes that can be transferred in an exclusive burst is 128. AMBA AXI and ACE Protocol Specification section A7.2.4.
AXI4_AWUSER_STABLE AWUSER must remain stable when AWVALID is asserted and AWREADY low. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_WUSER_STABLE WUSER must remain stable when WVALID is asserted and WREADY low. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_BUSER_STABLE BUSER must remain stable when BVALID is asserted and BREADY low. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_ARUSER_STABLE ARUSER must remain stable when ARVALID is asserted and ARREADY low. Spec: section A3.2.1.
AXI4_RUSER_STABLE RUSER must remain stable when RVALID is asserted and RREADY low. AMBA AXI and ACE Protocol Specification section A3.2.1.
AXI4_AWUSER_X When AWVALID is high, a value of X on AWUSER is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_WUSER_X When WVALID is high, a value of X on WUSER is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_BUSER_X When BVALID is high, a value of X on BUSER is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_ARUSER_X When ARVALID is high, a value of X on ARUSER is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_RUSER_X When RVALID is high, a value of X on RUSER is not permitted. AMBA AXI and ACE Protocol Specification section A3.2.2.
AXI4_AWUSER_TIEOFF AWUSER must be stable when AWUSER_WIDTH is set to 0.
AXI4_WUSER_TIEOFF WUSER must be stable when WUSER_WIDTH is set to 0.
AXI4_BUSER_TIEOFF BUSER must be stable when BUSER_WIDTH is set to 0.
AXI4_ARUSER_TIEOFF ARUSER must be stable when ARUSER_WIDTH is set to 0.
AXI4_RUSER_TIEOFF RUSER must be stable when RUSER_WIDTH is set to 0.
AXI4_AWID_TIEOFF AWID must be stable when ID_WIDTH is set to 0.
AXI4_BID_TIEOFF BID must be stable when ID_WIDTH is set to 0.
AXI4_ARID_TIEOFF ARID must be stable when ID_WIDTH is set to 0.
AXI4_RID_TIEOFF RID must be stable when ID_WIDTH is set to 0.
Level Two Title