Altera® AXI4 Bus Functional Model User Guides

ID 838773
Date 5/19/2025
Public
Document Table of Contents

1.1.4. Altera® AXI4 Memory-Mapped BFM SystemVerilog Packages

The Altera® AXI4 memory-mapped BFMs require the altera_lnsim_ver simulation library. altera_lnsim_ver provides the altera_axi_bfm_pkg and host_memory_class_pkg SystemVerilog packages that the BFMs require. You can import the packages into your testbench and drive AXI4 memory-mapped transactions using the provided sets of APIs.