Altera® AXI4 Bus Functional Model User Guides

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ID 838773
Date 5/19/2025
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Altera® AXI4 Memory-Mapped BFM User Guide 2. Altera® AXI4 Streaming BFM User Guide 3. Document Revision History of Altera® AXI4 Bus Functional Model User Guides A. API Translation: Mentor* VIP to Altera® AXI4 Memory-Mapped BFM
1. Altera® AXI4 Memory-Mapped BFM User Guide x
1.1. Altera® AXI4 Memory-Mapped BFM Overview 1.2. Altera® AXI4 Memory-Mapped BFM Architecture 1.3. Altera® AXI4 Memory-Mapped BFM Configuration and Interfaces 1.4. Using the Altera® AXI4 Memory-Mapped BFMs 1.5. Altera® AXI4 Memory-Mapped BFM API 1.6. Altera® AXI4 Memory-Mapped Assertions
1.1. Altera® AXI4 Memory-Mapped BFM Overview x
1.1.1. Altera® AXI4 Memory-Mapped Specification Support 1.1.2. Altera® AXI4 Memory-Mapped BFM Components 1.1.3. Altera® AXI4 Memory-Mapped Supported Features 1.1.4. Altera® AXI4 Memory-Mapped BFM SystemVerilog Packages 1.1.5. Altera® AXI4 Memory-Mapped BFM Supported Flows 1.1.6. Altera® AXI4 Memory-Mapped BFM Supported Simulators
1.2. Altera® AXI4 Memory-Mapped BFM Architecture x
1.2.1. Altera® AXI4 Memory-Mapped Manager BFM Architecture 1.2.2. Altera® AXI4 Memory-Mapped Subordinate BFM Architecture 1.2.3. Altera® AXI4 Memory-Mapped Monitor BFM Architecture 1.2.4. Altera® AXI4 Memory-Mapped BFM Transaction Class
1.2.4. Altera® AXI4 Memory-Mapped BFM Transaction Class x
1.2.4.1. Altera® AXI4 Transaction Information
1.3. Altera® AXI4 Memory-Mapped BFM Configuration and Interfaces x
1.3.1. Altera® AXI4 Memory-Mapped Manager BFM Configuration 1.3.2. Altera® AXI4 Memory-Mapped Manager BFM Interface 1.3.3. Altera® AXI4 Memory-Mapped Subordinate BFM Configuration 1.3.4. Altera® AXI4 Memory-Mapped Subordinate BFM Interface 1.3.5. Altera® AXI4-Lite Memory-Mapped Manager BFM Configuration 1.3.6. Altera® AXI4-Lite Memory-Mapped Manager BFM Interface 1.3.7. Altera® AXI4-Lite Memory-Mapped Subordinate BFM Configuration 1.3.8. Altera® AXI4-Lite Memory-Mapped Subordinate BFM Interface 1.3.9. Altera® AXI4 Memory-Mapped Inline Monitor Configuration 1.3.10. Altera® AXI4 Inline Monitor Interface
1.4. Using the Altera® AXI4 Memory-Mapped BFMs x
1.4.1. Using the Altera® AXI4 Memory-Mapped Manager BFM Flow 1.4.2. Using the Altera® AXI4 Memory-Mapped Subordinate BFM Flow 1.4.3. Using the Altera® AXI4 Memory-Mapped Monitor BFM Flow 1.4.4. Altera® AXI4 Memory-Mapped Manager RTL Implementation Example 1.4.5. Altera® AXI4 Memory-Mapped Manager Platform Designer BFM Implementation Example
1.5. Altera® AXI4 Memory-Mapped BFM API x
1.5.1. Altera® AXI4 Memory-Mapped BFM Configuration API 1.5.2. Altera® AXI4 Memory-Mapped BFM Reset API 1.5.3. Altera® AXI4 Memory-Mapped Manager Transaction Creation API 1.5.4. Altera® AXI4 Memory-Mapped Subordinate Transaction Creation API 1.5.5. Altera® AXI4 Memory-Mapped Transaction Configuration API 1.5.6. Altera® AXI4 Memory-Mapped BFM Transaction Execution API 1.5.7. Altera® AXI4 Memory-Mapped Host Memory API
2. Altera® AXI4 Streaming BFM User Guide x
2.1. Altera® AXI4 Streaming BFM Overview 2.2. Altera® AXI4 Streaming BFM Architecture 2.3. Altera® AXI4 Streaming BFM Configuration and Interfaces 2.4. Using the Altera® AXI4 Streaming BFMs 2.5. Altera® AXI4 Streaming BFM Packages, Classes, Interfaces, and Modules
2.1. Altera® AXI4 Streaming BFM Overview x
2.1.1. AXI4 Protocol Specification Support 2.1.2. Altera® AXI4 Streaming BFM Components 2.1.3. AXI4 Streaming Supported Features 2.1.4. Altera® AXI4 Streaming BFM SystemVerilog Packages 2.1.5. Altera® AXI4 Streaming BFM Supported Flows 2.1.6. Altera® AXI4 Streaming BFM Supported Simulators
2.2. Altera® AXI4 Streaming BFM Architecture x
2.2.1. Altera® AXI4 Streaming BFM Data Organization 2.2.2. AXI4 Streaming Data Transfer 2.2.3. Altera® AXI4 Streaming Transmitter BFM 2.2.4. Altera® AXI4 Streaming Receiver BFM
2.2.1. Altera® AXI4 Streaming BFM Data Organization x
2.2.1.1. Altera® AXI4 Streaming BFM Beats 2.2.1.2. Altera® AXI4 Streaming BFM Transfers 2.2.1.3. Altera® AXI4 Streaming BFM Packets
2.3. Altera® AXI4 Streaming BFM Configuration and Interfaces x
2.3.1. Altera® AXI4 Streaming Transmitter BFM Configuration 2.3.2. Altera® AXI4 Streaming Transmitter BFM Interfaces 2.3.3. Altera® AXI4 Streaming Receiver BFM Configuration 2.3.4. Altera® AXI4 Streaming Receiver BFM Interface
2.4. Using the Altera® AXI4 Streaming BFMs x
2.4.1. Using the Transmitter BFM Flow 2.4.2. Using the Receiver BFM Flow 2.4.3. Altera® AXI4 Streaming BFM Tools 2.4.4. Altera® AXI4 Streaming BFM RTL Example 2.4.5. Altera® AXI4 Streaming BFM Platform Designer Example
2.4.3. Altera® AXI4 Streaming BFM Tools x
2.4.3.1. Number Formatting 2.4.3.2. Transfer Printing 2.4.3.3. Transfer Comparison
2.5. Altera® AXI4 Streaming BFM Packages, Classes, Interfaces, and Modules x
2.5.1. Altera® AXI4 Streaming Common BFM Packages, Classes, Interfaces, and Modules 2.5.2. Altera® AXI4 Streaming Transmitter BFM Packages, Classes, and Modules 2.5.3. Altera® AXI4 Streaming Receiver BFM Packages, Classes, and Modules
2.5.1. Altera® AXI4 Streaming Common BFM Packages, Classes, Interfaces, and Modules x
2.5.1.1. Package axi4_stream_bfm_types_pkg 2.5.1.2. Package axi4_stream_bytes_class_pkg 2.5.1.3. Package axi4_stream_transfer_class_pkg 2.5.1.4. Package axi4_stream_packet_class_pkg
2.5.1.1. Package axi4_stream_bfm_types_pkg x
2.5.1.1.1. Typedefs 2.5.1.1.2. Utility Function num_formatter 2.5.1.1.3. Interface axi4_stream_if 2.5.1.1.4. AXI4 Streaming Interface Modports 2.5.1.1.5. Protocol-Checking Assertions
2.5.1.2. Package axi4_stream_bytes_class_pkg x
2.5.1.2.1. Class Axi4StreamBytes 2.5.1.2.2. Data Members in Axi4StreamBytes Class 2.5.1.2.3. Methods in Axi4StreamBytes Class 2.5.1.2.4. Class Axi4StreamBytesData 2.5.1.2.5. Methods in Axi4StreamBytesData Class 2.5.1.2.6. Class Axi4StreamBytesPosition 2.5.1.2.7. Methods in Axi4StreamBytesPosition Class 2.5.1.2.8. Class Axi4StreamBytesNull 2.5.1.2.9. Methods in Axi4StreamBytesNull Class 2.5.1.2.10. Class Axi4StreamBytesDataError 2.5.1.2.11. Data Members in Axi4StreamBytesDataError Class 2.5.1.2.12. Methods in Class Axi4StreamBytesDataError 2.5.1.2.13. Class Axi4StreamBytesPositionError 2.5.1.2.14. Data Members in Class Axi4StreamBytesPositionError 2.5.1.2.15. Methods in Class Axi4StreamBytesPositionError 2.5.1.2.16. Class Axi4StreamBytesNullError 2.5.1.2.17. Data Members in Class Axi4StreamBytesNullError 2.5.1.2.18. Methods in Class Axi4StreamBytesNullError
2.5.1.3. Package axi4_stream_transfer_class_pkg x
2.5.1.3.1. Class Axi4StreamTransfer 2.5.1.3.2. Data Members in Class Axi4StreamTransfer 2.5.1.3.3. Methods in Class Axi4StreamTransfer
2.5.1.4. Package axi4_stream_packet_class_pkg x
2.5.1.4.1. Class Axi4StreamPacket 2.5.1.4.2. Data Members in Class Axi4StreamPacket 2.5.1.4.3. Methods in Class Axi4StreamPacket
2.5.2. Altera® AXI4 Streaming Transmitter BFM Packages, Classes, and Modules x
2.5.2.1. Package axi4_stream_bfm_transmit_pkg.sv
2.5.2.1. Package axi4_stream_bfm_transmit_pkg.sv x
2.5.2.1.1. Class TransmitBFM 2.5.2.1.2. Module axi4_stream_bfm_transmit_top 2.5.2.1.3. Method Prototypes in Class TransmitBFM
2.5.3. Altera® AXI4 Streaming Receiver BFM Packages, Classes, and Modules x
2.5.3.1. Package axi4_stream_bfm_receive_pkg.sv
2.5.3.1. Package axi4_stream_bfm_receive_pkg.sv x
2.5.3.1.1. Class ReceiveBFM 2.5.3.1.2. Module axi4_stream_bfm_receive_top 2.5.3.1.3. Method Prototypes in Class ReceiveBFM
Answers to Top FAQs
1. Altera® AXI4 Memory-Mapped BFM User Guide
2. Altera® AXI4 Streaming BFM User Guide
3. Document Revision History of Altera® AXI4 Bus Functional Model User Guides
A. API Translation: Mentor* VIP to Altera® AXI4 Memory-Mapped BFM

1.3.10. Altera® AXI4 Inline Monitor Interface

interface altera_axi4_inline_monitor #(
	  parameter int ADDR_WIDTH = 64,
	  parameter int DATA_WIDTH = 32,
	  parameter int ID_WIDTH = 8, 
	  parameter int USER_WIDTH = 32,
	  parameter int USE_AXI4LITE = 0,
	  parameter int USE_AWID = 1,
      parameter int USE_AWREGION = 1,
      parameter int USE_AWLEN = 1,
      parameter int USE_AWSIZE = 1,
      parameter int USE_AWBURST = 1,
      parameter int USE_AWLOCK = 1,
      parameter int USE_AWCACHE = 1,
      parameter int USE_AWQOS = 1,
      parameter int USE_WSTRB = 1,
      parameter int USE_BID = 1,
      parameter int USE_AWPROT = 1,
      parameter int USE_WLAST = 1,
      parameter int USE_BRESP = 1,
      parameter int USE_ARID = 1,
      parameter int USE_ARREGION = 1,
      parameter int USE_ARLEN = 1,
      parameter int USE_ARSIZE = 1,
      parameter int USE_ARBURST = 1,
      parameter int USE_ARLOCK = 1,
      parameter int USE_ARCACHE = 1,
      parameter int USE_ARQOS = 1,
      parameter int USE_RID = 1,
      parameter int USE_ARPROT = 1,
      parameter int USE_RRESP = 1,
      parameter int USE_RLAST = 1,
      parameter int USE_AWUSER = 1,
      parameter int USE_ARUSER = 1,
      parameter int USE_WUSER = 1,
      parameter int USE_RUSER = 1,
      parameter int USE_BUSER = 1
)(
	  input ACLK, 
	  input ARESETn,

	  //Subordinate facing signals
	  output    [ID_WIDTH-1:0]           m_awid,
	  output    [ADDR_WIDTH-1:0]         m_awaddr,
	  output    [7:0]                    m_awlen,
	  output    [2:0]                    m_awsize,
	  output    [1:0]                    m_awburst,
	  output    [0:0]                    m_awlock,
	  output    [3:0]                    m_awcache,
	  output    [2:0]                    m_awprot,
	  output    [3:0]                    m_awqos,
	  output    [3:0]                    m_awregion,
	  output    [USER_WIDTH-1:0]         m_awuser,
	  output    [0:0]                    m_awvalid,
	  input     [0:0]                    m_awready,
	  output    [DATA_WIDTH-1:0]         m_wdata, 
      output    [((DATA_WIDTH/8)-1):0]   m_wstrb,	
      output    [0:0]                    m_wlast,	
      output    [USER_WIDTH-1:0]         m_wuser, 
      output    [0:0]                    m_wvalid,
	  input     [0:0]                    m_wready,
      input     [ID_WIDTH-1:0]           m_bid,	  
      input     [1:0]                    m_bresp, 
      input     [USER_WIDTH-1:0]         m_buser, 
      input     [0:0]                    m_bvalid,
	  output    [0:0]                    m_bready,	
      output    [ID_WIDTH-1:0]           m_arid,		
      output    [ADDR_WIDTH-1:0]         m_araddr, 	
      output    [7:0]                    m_arlen, 	
      output    [2:0]                    m_arsize, 	
      output    [1:0]                    m_arburst, 	
      output    [0:0]                    m_arlock,	
      output    [3:0]                    m_arcache, 	
      output    [2:0]                    m_arprot,	
      output    [3:0]                    m_arqos,   	
      output    [3:0]                    m_arregion,	
      output    [USER_WIDTH-1:0]         m_aruser,  	
      output    [0:0]                    m_arvalid,	
	  input     [0:0]                    m_arready, 	
      input     [ID_WIDTH-1:0]           m_rid,		
      input     [DATA_WIDTH-1:0]         m_rdata, 	
      input     [1:0]                    m_rresp, 	
      input     [0:0]                    m_rlast, 	
      input     [USER_WIDTH-1:0]         m_ruser, 	
      input     [0:0]                    m_rvalid,	
	  output    [0:0]                    m_rready,

	  //Manager facing signals 
	  input     [ID_WIDTH-1:0]           s_awid,
	  input     [ADDR_WIDTH-1:0]         s_awaddr,
	  input     [7:0]                    s_awlen,
	  input     [2:0]                    s_awsize,
	  input     [1:0]                    s_awburst,
	  input     [0:0]                    s_awlock,
	  input     [3:0]                    s_awcache,
	  input     [2:0]                    s_awprot,
	  input     [3:0]                    s_awqos,
	  input     [3:0]                    s_awregion,
	  input     [USER_WIDTH-1:0]         s_awuser,
	  input     [0:0]                    s_awvalid,
	  output    [0:0]                    s_awready,
	  input     [DATA_WIDTH-1:0]         s_wdata, 
      input     [((DATA_WIDTH/8)-1):0]   s_wstrb,	
      input     [0:0]                    s_wlast,	
      input     [USER_WIDTH-1:0]         s_wuser, 
      input     [0:0]                    s_wvalid,
	  output    [0:0]                    s_wready,
      output    [ID_WIDTH-1:0]           s_bid,	  
      output    [1:0]                    s_bresp, 
      output    [USER_WIDTH-1:0]         s_buser, 
      output    [0:0]                    s_bvalid,
	  input     [0:0]                    s_bready,	
      input     [ID_WIDTH-1:0]           s_arid,		
      input     [ADDR_WIDTH-1:0]         s_araddr, 	
      input     [7:0]                    s_arlen, 	
      input     [2:0]                    s_arsize, 	
      input     [1:0]                    s_arburst, 	
      input     [0:0]                    s_arlock,	
      input     [3:0]                    s_arcache, 	
      input     [2:0]                    s_arprot,	
      input     [3:0]                    s_arqos,   	
      input     [3:0]                    s_arregion,	
      input     [USER_WIDTH-1:0]         s_aruser,  	
      input     [0:0]                    s_arvalid,	
	  output    [0:0]                    s_arready, 	
      output    [ID_WIDTH-1:0]           s_rid,		
      output    [DATA_WIDTH-1:0]         s_rdata, 	
      output    [1:0]                    s_rresp, 	
      output    [0:0]                    s_rlast, 	
      output    [USER_WIDTH-1:0]         s_ruser, 	
      output    [0:0]                    s_rvalid,	
	  input     [0:0]                    s_rready
	);
Level Two Title