Altera® AXI4 Bus Functional Model User Guides

ID 838773
Date 5/19/2025
Public
Document Table of Contents

1.4.5. Altera® AXI4 Memory-Mapped Manager Platform Designer BFM Implementation Example

The following example testbench is a modification of the bfm_test_system_tb.v testbench that Platform Designer generates.

For guidance on generating testbench and simulation files, refer to Generating Simulation Files for Platform Designer Systems and IP Variants in Quartus® Prime Pro Edition User Guide: Platform Designer.

Figure 3. Platform Designer Example Testbench


// bfm_test_system_tb.v

// Generated using ACDS version XX.X.X.XX
// Add 
import altera_lnsim_ver.altera_axi_bfm_pkg::*;
import altera_lnsim_ver.host_memory_class_pkg::*;

// For simplicity, defining hierarchical names of manager and subordinate BFMs
// <PD system inst>.<PD bfm inst>.<bfm inst>
`define mgr_bfm bfm_test_system_inst.axi4_manager_bfm.axi4_mm_manager_intf_0
`define sub_bfm bfm_test_system_inst.axi4_subordinate_bfm.axi4_mm_subordinate_intf_0
// For simplicity, defining hierarchical names of subordinate host memory
// <PD system inst>.<PD bfm inst>.<bfm inst>.host_memory
`define sub_mem `sub_bfm.host_memory	

localparam ADDR_WIDTH = 64; 
localparam DATA_WIDTH = 64; 
localparam ID_WIDTH   = 8; 
localparam USER_WIDTH = 32;	 

// Testbench provided by Platform Designer
`timescale 1 ps / 1 ps
module bfm_test_system_tb (
   );
   
wire bfm_test_system_inst_clk_bfm_clk_clk;       
wire bfm_test_system_inst_reset_bfm_reset_reset; 

bfm_test_system_inst_clk_bfm_ip bfm_test_system_inst_clk_bfm (
   .clk (bfm_test_system_inst_clk_bfm_clk_clk)
);

bfm_test_system_inst_reset_bfm_ip bfm_test_system_inst_reset_bfm (
   .reset (bfm_test_system_inst_reset_bfm_reset_reset), 
   .clk   (bfm_test_system_inst_clk_bfm_clk_clk)        
);

 bfm_test_system bfm_test_system_inst (
    .clk_clk     (bfm_test_system_inst_clk_bfm_clk_clk),      
    .reset_reset (bfm_test_system_inst_reset_bfm_reset_reset) 
	);
// End of testbench provided by Platform Designer	

// BFM Manager	
initial begin
// AXI Transactions
AlteraAxiTransaction wr_tr, rd_tr; 

// Manager BFM 
BaseAxiBfm#(ADDR_WIDTH, DATA_WIDTH, ID_WIDTH, USER_WIDTH) axi_mgr_bfm;
 
axi_mgr_bfm = `mgr_bfm.AXI4MAN.bfm; 

// Reset BFM 
axi_mgr_bfm.m_reset();

// Create Read Transaction and configure
rd_tr = axi_mgr_bfm.manager_bfm_rd_tx(1, 0, 3, AXI4_BYTES_8, BURST_TYPE_INCR);
// id,  addr, burst_len, burst_size, burst_type

// Execute Read Transaction
axi_mgr_bfm.put_transaction(rd_tr);
axi_mgr_bfm.drive_transaction(); 

// Create Write Transaction
wr_tr = axi_mgr_bfm.manager_bfm_wr_tx();    

// Configure Write Transaction
wr_tr.set_id(1);
wr_tr.set_awaddr(0);
wr_tr.set_burst_length(3);
wr_tr.set_size(AXI4_BYTES_8);
wr_tr.set_burst_type(BURST_TYPE_INCR);
                    
wr_tr.set_data_words('haaaaaaaa_11111111, 0); // data, index
wr_tr.set_data_words('hbbbbbbbb_22222222, 1); 
wr_tr.set_data_words('hcccccccc_33333333, 2); 
wr_tr.set_data_words('hdddddddd_44444444, 3);
wr_tr.set_write_strobes(8'hff, 0); 		 //strobe, index
wr_tr.set_write_strobes(8'hff, 1);
wr_tr.set_write_strobes(8'hff, 2);
wr_tr.set_write_strobes(8'hff, 3);

// Execute Write Transaction
axi_mgr_bfm.put_transaction(wr_tr); 
axi_mgr_bfm.drive_transaction(); 

// Execute Read Transaction
rd_tr.set_id(2);
axi_mgr_bfm.put_transaction(rd_tr); 
axi_mgr_bfm.drive_transaction(); 

$display("\n@ *************** END OF Write/Read TEST ***************\n");
end // Manager BFM

// Subordinate BFM 
initial begin
AlteraAxiTransaction wr_resp_tr, rd_resp_tr; 
byte_t init_buf[]; 

BaseAxiBfm#(ADDR_WIDTH, DATA_WIDTH, ID_WIDTH, USER_WIDTH) axi_sub_bfm;
axi_sub_bfm = `sub_bfm.AXI4SUB.bfm;
 
//Reset BFM 
axi_sub_bfm.s_reset();

wr_resp_tr = axi_sub_bfm.subordinate_bfm_wr_resp_tx(); 
rd_resp_tr = axi_sub_bfm.subordinate_bfm_rd_resp_tx(); 

fork 
	//Initialise the memory 
	init_buf = new[8]; 
	
	init_buf = {<<byte_t{64'h0000_ffff_0000_ffff}};
	`sub_mem.initialize_data(0, init_buf); 
     init_buf = {<<byte_t{64'hffff_1111_ffff_1111}}; 
	`sub_mem.initialize_data(8, init_buf); 
	init_buf = {<<byte_t{64'h2222_ffff_2222_ffff}}; 
	`sub_mem.initialize_data(16, init_buf); 
     init_buf = {<<byte_t{64'h1111_2222_3333_4444}}; 
	`sub_mem.initialize_data(24, init_buf);
join 

fork 
	forever begin	
	axi_sub_bfm.put_transaction(rd_resp_tr);  		   
	axi_sub_bfm.drive_transaction();   
	end
	
	forever begin
	axi_sub_bfm.put_transaction(wr_resp_tr); 	 		   
	axi_sub_bfm.drive_transaction();   
	end
join 
end // Subordinate BFM

endmodule

The following shows the simulation output from this example:

Figure 4. Platform Designer Example Simulation Output