1.1.1. Altera® AXI4 Memory-Mapped Specification Support
1.1.2. Altera® AXI4 Memory-Mapped BFM Components
1.1.3. Altera® AXI4 Memory-Mapped Supported Features
1.1.4. Altera® AXI4 Memory-Mapped BFM SystemVerilog Packages
1.1.5. Altera® AXI4 Memory-Mapped BFM Supported Flows
1.1.6. Altera® AXI4 Memory-Mapped BFM Supported Simulators
1.3.1. Altera® AXI4 Memory-Mapped Manager BFM Configuration
1.3.2. Altera® AXI4 Memory-Mapped Manager BFM Interface
1.3.3. Altera® AXI4 Memory-Mapped Subordinate BFM Configuration
1.3.4. Altera® AXI4 Memory-Mapped Subordinate BFM Interface
1.3.5. Altera® AXI4-Lite Memory-Mapped Manager BFM Configuration
1.3.6. Altera® AXI4-Lite Memory-Mapped Manager BFM Interface
1.3.7. Altera® AXI4-Lite Memory-Mapped Subordinate BFM Configuration
1.3.8. Altera® AXI4-Lite Memory-Mapped Subordinate BFM Interface
1.3.9. Altera® AXI4 Memory-Mapped Inline Monitor Configuration
1.3.10. Altera® AXI4 Inline Monitor Interface
1.4.1. Using the Altera® AXI4 Memory-Mapped Manager BFM Flow
1.4.2. Using the Altera® AXI4 Memory-Mapped Subordinate BFM Flow
1.4.3. Using the Altera® AXI4 Memory-Mapped Monitor BFM Flow
1.4.4. Altera® AXI4 Memory-Mapped Manager RTL Implementation Example
1.4.5. Altera® AXI4 Memory-Mapped Manager Platform Designer BFM Implementation Example
1.5.1. Altera® AXI4 Memory-Mapped BFM Configuration API
1.5.2. Altera® AXI4 Memory-Mapped BFM Reset API
1.5.3. Altera® AXI4 Memory-Mapped Manager Transaction Creation API
1.5.4. Altera® AXI4 Memory-Mapped Subordinate Transaction Creation API
1.5.5. Altera® AXI4 Memory-Mapped Transaction Configuration API
1.5.6. Altera® AXI4 Memory-Mapped BFM Transaction Execution API
1.5.7. Altera® AXI4 Memory-Mapped Host Memory API
2.4.1. Using the Transmitter BFM Flow
2.4.2. Using the Receiver BFM Flow
IP Catalog Receiver BFM Generation Flow
Platform Designer Receiver BFM Generation Flow
Creating a Testbench using the AXI4 Streaming BFM
2.4.3. Altera® AXI4 Streaming BFM Tools
2.4.4. Altera® AXI4 Streaming BFM RTL Example
2.4.5. Altera® AXI4 Streaming BFM Platform Designer Example
2.5.1.2.1. Class Axi4StreamBytes
2.5.1.2.2. Data Members in Axi4StreamBytes Class
2.5.1.2.3. Methods in Axi4StreamBytes Class
2.5.1.2.4. Class Axi4StreamBytesData
2.5.1.2.5. Methods in Axi4StreamBytesData Class
2.5.1.2.6. Class Axi4StreamBytesPosition
2.5.1.2.7. Methods in Axi4StreamBytesPosition Class
2.5.1.2.8. Class Axi4StreamBytesNull
2.5.1.2.9. Methods in Axi4StreamBytesNull Class
2.5.1.2.10. Class Axi4StreamBytesDataError
2.5.1.2.11. Data Members in Axi4StreamBytesDataError Class
2.5.1.2.12. Methods in Class Axi4StreamBytesDataError
2.5.1.2.13. Class Axi4StreamBytesPositionError
2.5.1.2.14. Data Members in Class Axi4StreamBytesPositionError
2.5.1.2.15. Methods in Class Axi4StreamBytesPositionError
2.5.1.2.16. Class Axi4StreamBytesNullError
2.5.1.2.17. Data Members in Class Axi4StreamBytesNullError
2.5.1.2.18. Methods in Class Axi4StreamBytesNullError
2.4.2. Using the Receiver BFM Flow
The following steps describe implementation of the Receiver BFM from the Quartus® Prime Pro Edition software IP Catalog or from Platform Designer. You can use either the IP Catalog flow to define a single Receiver BFM and testbench, or use the Platform Designer flow to integrate the BFM and testbench into a Platform Designer system.
IP Catalog Receiver BFM Generation Flow
- From the Quartus® Prime Pro Edition software IP Catalog, search for the Altera AXI4 Streaming Receiver BFM.
- In the IP parameter editor, specify appropriate parameters and generate the HDL for your receiver configuration.
- Create a testbench and connect the Receiver BFM to the DUT.
- To access the Receiver BFM, use the following hierarchy:
<bfm inst>.axi4_stream_bfm_ receiver_0.axi4_stream_rx_bfm
Platform Designer Receiver BFM Generation Flow
- In the Quartus® Prime Pro Edition software, click Tools > Platform Designer.
- In Platform Designer's IP Catalog, search for the Altera AXI4 Streaming Receiver BFM.
- In the IP parameter editor, specify appropriate parameters for your receiver configuration.
- To generate the Platform Designer system and testbench, click Generate HDL.
- To access the Transmitter BFM in the testbench, use the following hierarchy:
<PD system inst>.<PD bfm inst>.<PD bfm inst>.axi4_stream_rx_bfm
Creating a Testbench using the AXI4 Streaming BFM
- Import the required Altera AXI4 Streaming BFM SystemVerilog packages:
import altera_lnsim_ver.axi4_stream_bfm_types_pkg::*; import altera_lnsim_ver.axi4_stream_bytes_class_pkg::*; import altera_lnsim_ver.axi4_stream_transfer_class_pkg::*; import altera_lnsim_ver.axi4_stream_packet_class_pkg::*;
- Create and receive transfers from the Receiver BFM:
// Receive Transfer Axi4StreamTransfer#(.AXI4_STREAMING_DATA_BUS_WIDTH(DATA_BUS_WIDTH), .AXI4_STREAMING_TID_WIDTH(TID_WIDTH), .AXI4_STREAMING_TDEST_WIDTH(TDEST_WIDTH), .AXI4_STREAMING_TUSER_WIDTH(TUSER_WIDTH)) rx_tr;
- Use either of the following methods to check the state of received transfers:
- Option 1: get_number_of_transfers_in_queue()—returns the number of transfers the receiver assembles and places them into an internal queue waiting for read out.
- Option 2: transfer_available()—returns a one if there are transfers available to be read out of the receiver. Otherwise, returns zero.
In the following code sample, the get_number_of_transfers_in_queue() method determines if expected transfers have arrived. Next, transfer_available() prints out all received transfers.
while (`bfm_rx.receive_bfm.get_number_of_transfers_in_queue() != NUM_TX_TFRS)) begin @(posedge axist_bfm_system_inst_clk_bfm_clk_clk); End while (`bfm_rx.receive_bfm.transfer_available()) begin rx_tr = `bfm_rx.receive_bfm.get_transfer_from_receive(); rx_tr.print_transfer_long(); end