Altera® AXI4 Bus Functional Model User Guides

ID 838773
Date 5/19/2025
Public
Document Table of Contents

1.3.5. Altera® AXI4-Lite Memory-Mapped Manager BFM Configuration

The following table describes the Altera® AXI4-Lite Memory-Mapped Manager BFM configuration parameters.

Table 10.  Altera AXI4-Lite Memory-Mapped Manager BFM Parameters
AXI4-Lite Memory-Mapped Parameter Description
ADDR_WIDTH The width of the AWADDR and ARADDR signals (refer to AMBA AXI and ACE Protocol Specification section A2.2).
DATA_WIDTH The width of the DATA signal (refer to AMBA AXI and ACE Protocol Specification section A2.6).