Visible to Intel only — GUID: jjm1685724982420
Ixiasoft
Visible to Intel only — GUID: jjm1685724982420
Ixiasoft
3.1.4. 999993: Multiple concurrent ECC errors might cause silent data corruption
Description
If multiple separate ECC errors are detected in the L1 data cache at around the same time, then in rare cases a store might write to an incorrect way and cause silent data corruption.
Conditions
- 1. An ECC error is detected in the L1 data cache tag or data RAMs by a store, a pagewalk, or a prefetch.
- 2. One or more store instructions are executed so that:
- * More than one 16-byte aligned region within a single cache line is written, which must be a different line to the one on which the ECC error in condition 1 was detected.
- * At least one of the regions is only partially written.
- 3. A single-bit ECC error is detected within a partially written 16-byte region written by condition 2.
Impact
There is still substantial benefit being gained from the ECC logic.
This erratum might cause a small increase in overall system failure rate.
The detection of the errors is still reported in the error record registers if they are configured to count correctable errors.
Workaround
No workaround is required.
Category
Category C