DisplayPort IP Design Example User Guide: Agilex™ 5 FPGAs

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ID 823560
Date 8/15/2025
Public
Document Table of Contents
Document Table of Contents x
1. DisplayPort IP Design Example Quick Start Guide 2. DisplayPort IP Design Examples 3. DisplayPort SST Parallel Loopback without PCR Design Example 4. DisplayPort SST Parallel Loopback with AXI4-S Video Interface Design Example 5. DisplayPort SST TX-Only Design Example 6. DisplayPort SST RX-Only Design Example 7. Document Revision History for the DisplayPort IP Design Example User Guide: Agilex™ 5 FPGAs
1. DisplayPort IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. Regenerating the Nios V .elf File 1.7. DisplayPort IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Premium Development Kit 1.5.2. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular Development Kit Connector with No FMC Mode 1.5.3. Compiling and Testing the Design Using Agilex™ 5 E-Series 065B Modular Development Kit Connecter with Bitec Rev 8 Daughter Card
2. DisplayPort IP Design Examples x
2.1. Design Components 2.2. DisplayPort IP Design Example Clock Domains 2.3. Interface Signals and Parameters 2.4. Simulation Testbench 2.5. DisplayPort Duplex or Dual Simplex Design Examples
2.5. DisplayPort Duplex or Dual Simplex Design Examples x
2.5.1. DisplayPort Duplex Designs 2.5.2. DisplayPort Dual-Simplex Designs
3. DisplayPort SST Parallel Loopback without PCR Design Example x
3.1. Features 3.2. Functional Description
4. DisplayPort SST Parallel Loopback with AXI4-S Video Interface Design Example x
4.1. Features 4.2. Functional Description
5. DisplayPort SST TX-Only Design Example x
5.1. DisplayPort SST TX-Only Features 5.2. DisplayPort SST TX-Only Functional Description
6. DisplayPort SST RX-Only Design Example x
6.1. DisplayPort SST RX-Only Features 6.2. DisplayPort SST RX-Only Functional Description
1. DisplayPort IP Design Example Quick Start Guide
2. DisplayPort IP Design Examples
3. DisplayPort SST Parallel Loopback without PCR Design Example
4. DisplayPort SST Parallel Loopback with AXI4-S Video Interface Design Example
5. DisplayPort SST TX-Only Design Example
6. DisplayPort SST RX-Only Design Example
7. Document Revision History for the DisplayPort IP Design Example User Guide: Agilex™ 5 FPGAs

4.2. Functional Description

For the DisplayPort SST parallel loopback with AXI4-S video interface design example.
Figure 14.  Agilex™ 5 DisplayPort SST Parallel Loopback with AXI4-S Video Interface
  • In this variant, the DisplayPort source and sink parameter, select AXIS-VVP FULL in Enable Active Video Data Protocols to enable AXI-Stream Video Data Interface.
  • The DisplayPort sink receives video and or audio streaming from external video source such as GPU and decodes it into parallel video interface.
  • The DisplayPort Sink converts video data stream into AXI4-Stream video data and drives the DisplayPort source AXI-Stream video data interface through video and vision Frame Buffer IP. The DisplayPort Source then converts AXI-Stream video data into DisplayPort main link before transmitting it to the monitor.
Note:
  • Because of restrictions of the Modular Kit board, the FPGA clock routes are not sufficient to support both the EMIF and SystemPLL transceiver modes simultaneously. This limitation does not apply to the Premium development kit.
  • When targeting the modular development kit, turning on System PLL in the design example GUI generates an error message. The design example does not support this combination, because of device routing limitations.
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