GTS HDMI IP User Guide

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ID 823533
Date 5/30/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS HDMI IP Quick Reference 2. About the GTS HDMI IP 3. GTS HDMI IP Getting Started 4. GTS HDMI IP Hardware Design Examples 5. HDMI Source 6. HDMI Sink 7. Transceiver Handling (HDMI Wrapper = HDMI and Transceiver) 8. GTS HDMI IP Parameters 9. HDMI Simulation Example 10. GTS HDMI IP User Guide Archives 11. Document Revision History for the GTS HDMI IP User Guide
1. GTS HDMI IP Quick Reference x
1.1. Terms and Acronyms
2. About the GTS HDMI IP x
2.1. GTS HDMI IP Device Family Support 2.2. GTS HDMI IP Device Feature Support 2.3. GTS HDMI IP Release Information 2.4. GTS HDMI IP Performance and Resource Usage
3. GTS HDMI IP Getting Started x
3.1. Installing and Licensing IP Cores 3.2. Specifying IP Parameters and Options
3.1. Installing and Licensing IP Cores x
3.1.1. Intel FPGA IP Evaluation Mode
5. HDMI Source x
5.1. Source Functional Description 5.2. Source Interfaces 5.3. Source Clock Tree 5.4. Valid Video Data 5.5. Source Deep Color Implementation
5.1. Source Functional Description x
5.1.1. Source Scrambler, TMDS/TERC4 Encoder 5.1.2. Source Video Resampler 5.1.3. Source Window of Opportunity Generator 5.1.4. Source Auxiliary Packet Encoder 5.1.5. Source Auxiliary Packet Generators 5.1.6. Source Auxiliary Data Path Multiplexers 5.1.7. Source Auxiliary Control Port 5.1.8. Source Audio Encoder 5.1.9. TX Core-PHY Interface 5.1.10. I2C Controller
5.1.7. Source Auxiliary Control Port x
5.1.7.1. Source General Control Packet (GCP) 5.1.7.2. Source Auxiliary Video Information (AVI) InfoFrame Bit-Fields 5.1.7.3. Source HDMI Vendor Specific InfoFrame (VSI)
5.1.8. Source Audio Encoder x
5.1.8.1. Audio InfoFrame (AI) Bundle Bit-Fields 5.1.8.2. Audio Metadata Bundle Bit-Fields
5.1.9. TX Core-PHY Interface x
5.1.9.1. TX Oversampler 5.1.9.2. Clock Enable Generator
6. HDMI Sink x
6.1. Sink Functional Description 6.2. Sink Interfaces 6.3. Sink Clock Tree 6.4. Sink Deep Color Implementation
6.1. Sink Functional Description x
6.1.1. Sink Word Alignment and Channel Deskew 6.1.2. Sink Descrambler, TMDS/TERC4 Decoder 6.1.3. Sink Auxiliary Decoder 6.1.4. Sink Auxiliary Packet Capture 6.1.5. Sink Video Resampler 6.1.6. Sink Auxiliary Data Port 6.1.7. Sink Audio Decoder 6.1.8. Status and Control Data Channel (SCDC) Interface 6.1.9. RX Core-PHY Interface 6.1.10. I2C Target 6.1.11. I2C and EDID RAM Blocks
6.1.6. Sink Auxiliary Data Port x
6.1.6.1. Sink General Control Packet (GCP) 6.1.6.2. Sink Auxiliary Video Information (AVI) InfoFrame Bit-Fields 6.1.6.3. Sink HDMI Vendor Specific InfoFrame (VSI)
6.1.7. Sink Audio Decoder x
6.1.7.1. Audio InfoFrame (AI) Bundle Bit-Fields 6.1.7.2. Audio Metadata Bundle Bit-Fields
6.1.9. RX Core-PHY Interface x
6.1.9.1. RX Oversampler
7. Transceiver Handling (HDMI Wrapper = HDMI and Transceiver) x
7.1. HDMI RX with Integrated Transceiver 7.2. HDMI TX with Integrated Transceiver 7.3. Creating Dual Simplex Groups
8. GTS HDMI IP Parameters x
8.1. HDMI Source Parameters 8.2. HDMI Sink Parameters
9. HDMI Simulation Example x
9.1. Simulation Walkthrough
1. GTS HDMI IP Quick Reference
2. About the GTS HDMI IP
3. GTS HDMI IP Getting Started
4. GTS HDMI IP Hardware Design Examples
5. HDMI Source
6. HDMI Sink
7. Transceiver Handling (HDMI Wrapper = HDMI and Transceiver)
8. GTS HDMI IP Parameters
9. HDMI Simulation Example
10. GTS HDMI IP User Guide Archives
11. Document Revision History for the GTS HDMI IP User Guide

1.1. Terms and Acronyms

Table 2.  Acronyms
Acronym Definition
AI Audio InfoFrame
AM Audio Metadata
AVI Auxiliary Video Information
AXI2CV AXI4-Stream to Clocked Video Converter
BPC Bit Per Component
BPP Bit Per Pixel
CEC Consumer Electronics Control
CV2AXI Clocked Video to AXI4-Stream Converter
DDC Display Data Channel
DVI Digital Visual Interface
EDID Extended Display Identification Data
FFE Feed forward error
FRL Fixed Rate Link
GCP General Control Packet
HDMI High-Definition Multimedia Interface
HPD Hotplug Detect
LPCM Linear Pulse Code Modulation
LTS Link Training State
RO Read Only Access
RW Read and Write Access
SCDC Status and Control Data Channel
TERC4 TMDS Error Reduction Coding - 4 bit
TMDS Transition Minimized Differential Signaling
VESA Video Electronics Standards Association
VSI Vendor Specific InfoFrame
W1C Write 1 to Clear the register bit
Level Two Title