1. GTS HDMI IP Quick Reference
2. About the GTS HDMI IP
3. GTS HDMI IP Getting Started
4. GTS HDMI IP Hardware Design Examples
5. HDMI Source
6. HDMI Sink
7. Transceiver Handling (HDMI Wrapper = HDMI and Transceiver)
8. GTS HDMI IP Parameters
9. HDMI Simulation Example
10. GTS HDMI IP User Guide Archives
11. Document Revision History for the GTS HDMI IP User Guide
5.1.1. Source Scrambler, TMDS/TERC4 Encoder
5.1.2. Source Video Resampler
5.1.3. Source Window of Opportunity Generator
5.1.4. Source Auxiliary Packet Encoder
5.1.5. Source Auxiliary Packet Generators
5.1.6. Source Auxiliary Data Path Multiplexers
5.1.7. Source Auxiliary Control Port
5.1.8. Source Audio Encoder
5.1.9. TX Core-PHY Interface
5.1.10. I2C Controller
6.1.1. Sink Word Alignment and Channel Deskew
6.1.2. Sink Descrambler, TMDS/TERC4 Decoder
6.1.3. Sink Auxiliary Decoder
6.1.4. Sink Auxiliary Packet Capture
6.1.5. Sink Video Resampler
6.1.6. Sink Auxiliary Data Port
6.1.7. Sink Audio Decoder
6.1.8. Status and Control Data Channel (SCDC) Interface
6.1.9. RX Core-PHY Interface
6.1.10. I2C Target
6.1.11. I2C and EDID RAM Blocks
6.1.10. I2C Target
The core includes a pair of I2C targets when you turn on the Include I2C Master/Slave parameter.
- One target is for the EDID address (0x50).
You need to instantiate a separate memory (ROM/RAM) to interface with this target. The HDMI IP also has an optional feature to include a RAM for EDID.
- The other target is for the SCDC address (0x54).
The I2C target for the SCDC will be directly interfaced with the HDMI core for the SCDC registers operation.
The Include I2C Pads parameter enables the instantiation of open-drain driver pads in the IP component. If this parameter is turned off, then these pads must be included at the system top-level.