GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 817713
Date 1/24/2025
Public
Document Table of Contents

1.2.2.5. Width Adapter

Width Adapter converts the Avalon® streaming interface signals from 256 bits to 512 bits for 256-bit PIO design example variant. This adaptation is to maintain data bandwidth to reuse the existing Bursting Avalon® Master architecture and to interface between the two clock domains. In the 512 bit PIO design example variant, no width adaptation is required, but there is logic between the adapter and to convert one segment of the AXI interface to two segments of the AVST interface in order to reuse the existing bursting Avalon® master architecture.

Features like TX and RX Credit Interface, Error Interface, FLR Interface, CII Interface, and Interrupt Interface are not used in the design example.