GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 817713
Date 1/24/2025
Public
Document Table of Contents

1.2. Programmed Input/Output Design Example Functional Description

Figure 2.  Platform Designer System Contents for the GTS AXI Streaming IP PIO Design Example ( PCIe* 4.0 x4 Variant)
Figure 3.  Platform Designer System Contents for the GTS AXI Streaming IP PIO Design Example ( PCIe* 4.0 x8 Variant)