F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide

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ID 815243
Date 5/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. F-Tile Low Latency 100G Ethernet Design Example Description 3. F-Tile Low Latency 100G Ethernet Intel FPGA IP Design Example User Guide Archives 4. Document Revision History for the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Command Line IP Generation Flow 1.4. Generating Tile Files 1.5. Simulating the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. F-Tile Low Latency 100G Ethernet Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Compilation 2.6. Hardware Testing 2.7. Design Example Registers 2.8. Design Example Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench 2.4.2. Simulation Design Example Components 2.4.3. Test Case
2.6. Hardware Testing x
2.6.1. Test Procedure
1. Quick Start Guide
2. F-Tile Low Latency 100G Ethernet Design Example Description
3. F-Tile Low Latency 100G Ethernet Intel FPGA IP Design Example User Guide Archives
4. Document Revision History for the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide

1.6. Compiling and Configuring the Design Example in Hardware

The F-Tile Low Latency 100G Ethernet Intel® FPGA IP parameter editor allows you to compile and configure the design example on a target development kit.
To compile and configure a design example on hardware, follow these steps:
  1. Launch the Quartus® Prime Pro Edition software and select Processing > Start Compilation to compile the design.
  2. After you generate an SRAM object file .sof, follow these steps to program the hardware design example on the Agilex™ 7 device:
    1. Select Tools > Programmer.
    2. In the Programmer, click Hardware Setup.
    3. Select a programming device.
    4. Select and add the Agilex™ 7 device to your Quartus® Prime Pro Edition session.
    5. Ensure that Mode is set to JTAG.
    6. Select the Intel device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
    7. In the row with your .sof, check the box for the .sof.
    8. Turn on Program/Configure option for the .sof.
    9. Click Start.
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