F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide

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ID 815243
Date 5/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. F-Tile Low Latency 100G Ethernet Design Example Description 3. F-Tile Low Latency 100G Ethernet Intel FPGA IP Design Example User Guide Archives 4. Document Revision History for the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Command Line IP Generation Flow 1.4. Generating Tile Files 1.5. Simulating the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. F-Tile Low Latency 100G Ethernet Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Compilation 2.6. Hardware Testing 2.7. Design Example Registers 2.8. Design Example Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench 2.4.2. Simulation Design Example Components 2.4.3. Test Case
2.6. Hardware Testing x
2.6.1. Test Procedure
1. Quick Start Guide
2. F-Tile Low Latency 100G Ethernet Design Example Description
3. F-Tile Low Latency 100G Ethernet Intel FPGA IP Design Example User Guide Archives
4. Document Revision History for the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide

4. Document Revision History for the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide

Document Version Quartus® Prime Version IP Version Changes
2025.05.07 25.1 6.0.0 Added support for Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit (Production 2 4× F-Tile).
  • Updated Generating the Design Example.
  • Updated Example Design Tab in the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Parameter Editor figure.
  • Updated Parameters in the Example Design Tab table.
  • Updated the Hardware and Software Requirements topic.
2025.02.21 24.3.1 5.0.0 Made the following changes:
  • Updated the following in Generating the Design Example section.
    • Example Design Tab GUI
    • Corrected the board name under Target Development Kit
  • Corrected the board name under Target Development Kit in the Design Example Parameters section.
  • Corrected the board name for hardware testing in the Hardware and Software Requirements section.
  • Added Connect the QSFP-DD Loopback Module to J27 in the Hardware and Software Requirements section.
  • Updated the F-Tile Low Latency 100G Ethernet Intel FPGA IP Design Example Block Diagram in the Functional Description section.

  • Updated the F-Tile Low Latency 100G Ethernet Design Example Simulation Testbench Block Diagram in the Testbench section.

2024.04.01 24.1 2.0.0 Initial release.
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