F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide

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ID 815243
Date 5/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. F-Tile Low Latency 100G Ethernet Design Example Description 3. F-Tile Low Latency 100G Ethernet Intel FPGA IP Design Example User Guide Archives 4. Document Revision History for the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Command Line IP Generation Flow 1.4. Generating Tile Files 1.5. Simulating the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. F-Tile Low Latency 100G Ethernet Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Compilation 2.6. Hardware Testing 2.7. Design Example Registers 2.8. Design Example Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench 2.4.2. Simulation Design Example Components 2.4.3. Test Case
2.6. Hardware Testing x
2.6.1. Test Procedure
1. Quick Start Guide
2. F-Tile Low Latency 100G Ethernet Design Example Description
3. F-Tile Low Latency 100G Ethernet Intel FPGA IP Design Example User Guide Archives
4. Document Revision History for the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide

1.2.1. Design Example Parameters

Table 2.  Parameters in the Example Design Tab
Parameter Description
Select Design Available example designs for the IP parameter settings.

Single Instance of IP Core: Example design instantiates a single instance of the IP.

Example Design Files

The files to generate for the different development phase.

  • Simulation: Generates the necessary files for simulating the example design.
  • Synthesis: Generates the synthesis files. Use these files to compile the design in the Quartus® Prime Pro Edition software for hardware testing and perform static timing analysis.
Generate File Format The format of the RTL files for simulation—Verilog or VHDL.
Select Board

Provides supports for various development kits listed. The details of Intel FPGA development kits can be found on the Intel FPGA website.

If this menu is greyed out, it is because no board is supported for the options selected such as synthesis checked off.

If an Intel FPGA development board is selected, the Target Device used for generation matches the device on the development kit.

Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit (Production 1 4× F-Tile) or Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit (Production 2 4× F-Tile) : This option allows you to test the design example on the selected Intel FPGA IP development kit. This option automatically selects the Target Device to match the device on the Intel FPGA IP development kit. If your board revision has a different device grade, you can change the target device.

None: This option excludes the hardware aspects for the design example.

Level Two Title