F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide

Download PDF
ID 815243
Date 5/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. F-Tile Low Latency 100G Ethernet Design Example Description 3. F-Tile Low Latency 100G Ethernet Intel FPGA IP Design Example User Guide Archives 4. Document Revision History for the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Command Line IP Generation Flow 1.4. Generating Tile Files 1.5. Simulating the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. F-Tile Low Latency 100G Ethernet Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Compilation 2.6. Hardware Testing 2.7. Design Example Registers 2.8. Design Example Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench 2.4.2. Simulation Design Example Components 2.4.3. Test Case
2.6. Hardware Testing x
2.6.1. Test Procedure
1. Quick Start Guide
2. F-Tile Low Latency 100G Ethernet Design Example Description
3. F-Tile Low Latency 100G Ethernet Intel FPGA IP Design Example User Guide Archives
4. Document Revision History for the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide

1.7. Testing the Design Example in Hardware

After you compile the F-Tile Low Latency 100G Ethernet Intel® FPGA IP design example and configure it on your Agilex™ 7 device, you can use the System Console to program the IP.

To turn on the System Console and test the hardware design example, follow these steps:

  1. In the Quartus® Prime Pro Edition software, select Tools > System Debugging Tools > System Console to launch the system console.
  2. In the Tcl Console pane, type cd hwtest to change directory to /hardware_test_design/hwtest.
  3. Type source main.tcl to open a connection to the JTAG master.
Follow the test procedure in the Hardware Testing section of the design example and observe the test results in the System Console.
Related Information
Level Two Title