Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs
A newer version of this document is available. Customers should click here to go to the newest version.
Visible to Intel only — GUID: qwr1674511906934
Ixiasoft
Visible to Intel only — GUID: qwr1674511906934
Ixiasoft
5.3.7. NAND Flash Controller Programming Model
This chapter guides the software developers on how to correctly operate the NAND Flash controller to achieve the best performance in the easiest possible way. The following sections complement the information presented earlier in this document.
Section Content
NAND Controller Registers Programming Model
Status Polling Configuration
Device Layout Configuration
Configure Multiplane and Cache Operations
ECC Enabling
Interrupts Configuration
Configuring Timing Registers
Switch from SDR to DDR Operation Mode
Switch from DDR to SDR Operation Mode
Slave DMA Programming
Data Pre-Fetching Mechanism
Data Integrity Mechanism
Enabling pSLC Mode for the TLC Devices