Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs
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5.8.5.2. FPGA Routing
The following figure shows the I3C controller FPGA routing interface signal.
The following table shows the I3C controller FPGA routing interface.
Signal Name | Signal Width | Direction | Direction |
---|---|---|---|
I3C<#>_sda_pullup_en | 1 | Out | SDA Open-Drain Pull-Up Signal Only applicable in master mode of operation. This signal enables the pull-up resistor or equivalent current source in open-drain mode when the controller requires to drive '1' on the SDA line |
I3C<#>_sda_out | 1 | Out | SDA Output Signal This signal is an input to the SDA pAD driver. |
I3C<#>_sda_oe | 1 | Out | Outgoing SDA Pad Enable This signal is used to enable the pad to switch between OD(0) and PP(1) mode. |
I3C<#>_sda_in_a | 1 | In | Incoming SDA Input SDA signal from the SDA pad driver |
I3C<#>_scl_pullup_en | 1 | Out | SCL Open-Drain Pull-Up Signal Applicable only in master mode of operation. This signal enables the pull-up resistor or equivalent current source in open-drain mode when the controller requires to drive '1' on the SCL line. |
I3C<#>_scl_out | 1 | Out | SCL output Signal This signal is an input to the SCL PAD Driver. |
I3C<#>_scl_oe | 1 | Out | Outgoing SCL Pad enable This signal is used to enable the Pad to switch between OD (0) and PP(1) mode. |
I3C<#>_scl_in_a | 1 | In | Incoming SCL Input SCL Signal from the SCL Pad Driver |