Triple-Speed Ethernet IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

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ID 813899
Date 8/04/2025
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Document Table of Contents
Document Table of Contents x
1. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver 2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS) 3. 10/100/1000 Ethernet MAC without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (GTS) with IEEE 1588v2 4. 10/100/1000 Ethernet MAC without Internal FIFO Buffers with 1000BASE-X/SGMII TBI PCS and Embedded PMA Signals (LVDS I/O) with IEEE 1588v2 5. Triple-Speed Ethernet IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives 6. Document Revision History for the Triple-Speed Ethernet IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
1. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver x
1.1. Quick Start Guide 1.2. Design Example Description
1.1. Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design Example 1.1.3. Simulating the Design Example Testbench 1.1.4. Compiling and Configuring the Design Example in Hardware
1.1.2. Generating the Design Example x
1.1.2.1. Design Example Parameters
1.2. Design Example Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Functional Description 1.2.4. Simulation 1.2.5. Hardware Testing 1.2.6. Interface Signals
1.2.3. Functional Description x
1.2.3.1. Design Components 1.2.3.2. Clock Signals
1.2.4. Simulation x
1.2.4.1. Testbench
1.2.5. Hardware Testing x
1.2.5.1. Test Procedure
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS) x
2.1. Quick Start Guide 2.2. Design Example Description
2.1. Quick Start Guide x
2.1.1. Directory Structure 2.1.2. Generating the Design Example 2.1.3. Simulating the Design Example Testbench 2.1.4. Compiling the Design Example
2.1.2. Generating the Design Example x
2.1.2.1. Design Example Parameters
2.2. Design Example Description x
2.2.1. Features 2.2.2. Hardware and Software Requirements 2.2.3. Functional Description 2.2.4. Simulation 2.2.5. Interface Signals
2.2.3. Functional Description x
2.2.3.1. Design Components 2.2.3.2. Clock Signals
2.2.4. Simulation x
2.2.4.1. Testbench
3. 10/100/1000 Ethernet MAC without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (GTS) with IEEE 1588v2 x
3.1. Quick Start Guide 3.2. Design Example Description
3.1. Quick Start Guide x
3.1.1. Directory Structure 3.1.2. Generating the Design Example 3.1.3. Simulating the Design Example Testbench 3.1.4. Compiling the Design Example in Hardware
3.1.2. Generating the Design Example x
3.1.2.1. Design Example Parameters
3.2. Design Example Description x
3.2.1. Features 3.2.2. Hardware and Software Requirements 3.2.3. Functional Description 3.2.4. Simulation 3.2.5. Hardware Testing 3.2.6. Interface Signals
3.2.3. Functional Description x
3.2.3.1. Design Components 3.2.3.2. Clock Signals
3.2.4. Simulation x
3.2.4.1. Testbench
3.2.5. Hardware Testing x
3.2.5.1. Test Procedure
4. 10/100/1000 Ethernet MAC without Internal FIFO Buffers with 1000BASE-X/SGMII TBI PCS and Embedded PMA Signals (LVDS I/O) with IEEE 1588v2 x
4.1. Quick Start Guide 4.2. Design Example Description
4.1. Quick Start Guide x
4.1.1. Directory Structure 4.1.2. Generating the Design Example 4.1.3. Simulating the Design Example Testbench 4.1.4. Compiling the Design Example
4.1.2. Generating the Design Example x
4.1.2.1. Design Example Parameters
4.2. Design Example Description x
4.2.1. Features 4.2.2. Hardware and Software Requirements 4.2.3. Functional Description 4.2.4. Simulation 4.2.5. Interface Signals
4.2.3. Functional Description x
4.2.3.1. Design Components 4.2.3.2. Clock Signals
4.2.4. Simulation x
4.2.4.1. Testbench
1. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS)
3. 10/100/1000 Ethernet MAC without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (GTS) with IEEE 1588v2
4. 10/100/1000 Ethernet MAC without Internal FIFO Buffers with 1000BASE-X/SGMII TBI PCS and Embedded PMA Signals (LVDS I/O) with IEEE 1588v2
5. Triple-Speed Ethernet IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives
6. Document Revision History for the Triple-Speed Ethernet IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

4.1.3. Simulating the Design Example Testbench

Figure 30. Procedure to Simulate Design Example Testbench

Follow these steps to simulate the testbench:

  1. Navigate to the testbench simulation directory:
    cd intel_eth_tse_0_example_design/example_testbench/
  2. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Refer to the table Steps to Simulate the Testbench.
    Table 25.  Steps to Simulate the Testbench
    Simulator Working Directory Command
    ModelSim* <Example Design>/example_testbench/mentor

    In the command line, type vsim -c -do run_vsim_lvds.do 1

    In the command line, type vsim -c -do run_vsim_mp_lvds.do 2
    Synopsys* VCS* MX <Example Design>/example_testbench/synopsys/vcsmx

    In the command line, type sh tb_run_lvds.sh 1

    In the command line, type sh tb_run_mp_lvds.sh 2
    Xcelium* <Example Design>/example_testbench/xcelium

    In the command line, type sh tb_run_lvds.sh 1

    In the command line, type sh tb_run_mp_lvds.sh 2
    Riviera-PRO* <Example Design>/example_testbench/aldec

    In the command line, type vsim -c -do tb_run_lvds.tcl 1

    In the command line, type vsim -c -do tb_run_mp_lvds.tcl 2
  3. Analyze the results. The successful testbench sends five packets, receives the same number of packets, and displays the following message:
    Simulation Passed
1 For single channel design (Number of ports parameter under the Core Configuration tab set to 1).
2 For multi channel design (Number of ports parameter under the Core Configuration tab set to 4)
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