Triple-Speed Ethernet IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

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ID 813899
Date 8/04/2025
Public
Document Table of Contents
Document Table of Contents x
1. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver 2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS) 3. 10/100/1000 Ethernet MAC without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (GTS) with IEEE 1588v2 4. 10/100/1000 Ethernet MAC without Internal FIFO Buffers with 1000BASE-X/SGMII TBI PCS and Embedded PMA Signals (LVDS I/O) with IEEE 1588v2 5. Triple-Speed Ethernet IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives 6. Document Revision History for the Triple-Speed Ethernet IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
1. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver x
1.1. Quick Start Guide 1.2. Design Example Description
1.1. Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design Example 1.1.3. Simulating the Design Example Testbench 1.1.4. Compiling and Configuring the Design Example in Hardware
1.1.2. Generating the Design Example x
1.1.2.1. Design Example Parameters
1.2. Design Example Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Functional Description 1.2.4. Simulation 1.2.5. Hardware Testing 1.2.6. Interface Signals
1.2.3. Functional Description x
1.2.3.1. Design Components 1.2.3.2. Clock Signals
1.2.4. Simulation x
1.2.4.1. Testbench
1.2.5. Hardware Testing x
1.2.5.1. Test Procedure
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS) x
2.1. Quick Start Guide 2.2. Design Example Description
2.1. Quick Start Guide x
2.1.1. Directory Structure 2.1.2. Generating the Design Example 2.1.3. Simulating the Design Example Testbench 2.1.4. Compiling the Design Example
2.1.2. Generating the Design Example x
2.1.2.1. Design Example Parameters
2.2. Design Example Description x
2.2.1. Features 2.2.2. Hardware and Software Requirements 2.2.3. Functional Description 2.2.4. Simulation 2.2.5. Interface Signals
2.2.3. Functional Description x
2.2.3.1. Design Components 2.2.3.2. Clock Signals
2.2.4. Simulation x
2.2.4.1. Testbench
3. 10/100/1000 Ethernet MAC without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (GTS) with IEEE 1588v2 x
3.1. Quick Start Guide 3.2. Design Example Description
3.1. Quick Start Guide x
3.1.1. Directory Structure 3.1.2. Generating the Design Example 3.1.3. Simulating the Design Example Testbench 3.1.4. Compiling the Design Example in Hardware
3.1.2. Generating the Design Example x
3.1.2.1. Design Example Parameters
3.2. Design Example Description x
3.2.1. Features 3.2.2. Hardware and Software Requirements 3.2.3. Functional Description 3.2.4. Simulation 3.2.5. Hardware Testing 3.2.6. Interface Signals
3.2.3. Functional Description x
3.2.3.1. Design Components 3.2.3.2. Clock Signals
3.2.4. Simulation x
3.2.4.1. Testbench
3.2.5. Hardware Testing x
3.2.5.1. Test Procedure
4. 10/100/1000 Ethernet MAC without Internal FIFO Buffers with 1000BASE-X/SGMII TBI PCS and Embedded PMA Signals (LVDS I/O) with IEEE 1588v2 x
4.1. Quick Start Guide 4.2. Design Example Description
4.1. Quick Start Guide x
4.1.1. Directory Structure 4.1.2. Generating the Design Example 4.1.3. Simulating the Design Example Testbench 4.1.4. Compiling the Design Example
4.1.2. Generating the Design Example x
4.1.2.1. Design Example Parameters
4.2. Design Example Description x
4.2.1. Features 4.2.2. Hardware and Software Requirements 4.2.3. Functional Description 4.2.4. Simulation 4.2.5. Interface Signals
4.2.3. Functional Description x
4.2.3.1. Design Components 4.2.3.2. Clock Signals
4.2.4. Simulation x
4.2.4.1. Testbench
1. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA (LVDS)
3. 10/100/1000 Ethernet MAC without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (GTS) with IEEE 1588v2
4. 10/100/1000 Ethernet MAC without Internal FIFO Buffers with 1000BASE-X/SGMII TBI PCS and Embedded PMA Signals (LVDS I/O) with IEEE 1588v2
5. Triple-Speed Ethernet IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives
6. Document Revision History for the Triple-Speed Ethernet IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

1. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver

Updated for:
Intel® Quartus® Prime Design Suite 25.1.1
IP Version 9.0.0

This design example demonstrates an Ethernet solution for Agilex™ 3 and Agilex™ 5 devices using the Triple-Speed Ethernet IP. You can generate the design from the Example Design tab of the Triple-Speed Ethernet IP parameter editor.

To generate the design example, you must first set the parameter values for the IP variation you intend to generate in your end product. Generating the design example creates a copy of the IP. The testbench and hardware design example uses the copy of the IP as the device under test (DUT). If you do not set the parameter values for the DUT to match the parameter values in your end product, the design example you generate does not exercise the IP variation that you intend.

Note: The testbench demonstrates a basic test of the IP. It is not intended to be a substitute for a full verification environment. You must perform more extensive verifications of your own Triple-Speed Ethernet design in simulation and in hardware.

Section Content
Quick Start Guide
Design Example Description

Level Two Title