Low Latency Ethernet 10G MAC IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

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ID 813665
Date 8/04/2025
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10M/100M/1G/2.5G Ethernet Design Example 3. 10M/100M/1G/2.5G/10G Ethernet Design Example 4. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature 5. 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature 6. 2.5G Ethernet Design Example 7. 2.5G Ethernet Design Example with IEEE 1588v2 Feature 8. 10M/100M/1G/2.5G/10G MGE (Multi Gigabit Ethernet) PCS Only Ethernet Design Example 9. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example 10. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588v2 Feature 11. Interface Signals Description 12. Configuration Registers Description 13. Low Latency Ethernet 10G MAC IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives 14. Document Revision History for the Low Latency Ethernet 10G MAC IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Signal Tap Debugging
1.2. Generating the Design x
1.2.1. Procedure 1.2.2. Design Example Parameters
1.3. Simulating the Design x
1.3.1. Procedure 1.3.2. Testbench
1.4. Compiling and Configuring the Design Example in Hardware x
1.4.1. Procedure 1.4.2. Hardware Setup
1.5. Signal Tap Debugging x
1.5.1. Signals Description 1.5.2. Signals List
2. 10M/100M/1G/2.5G Ethernet Design Example x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals 2.7. Configuration Registers
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme 2.3.3. Reset Scheme
2.5. Hardware Testing x
2.5.1. Test Procedure
3. 10M/100M/1G/2.5G/10G Ethernet Design Example x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing 3.6. Interface Signals 3.7. Configuration Registers
3.3. Functional Description x
3.3.1. Design Components 3.3.2. Clocking Scheme 3.3.3. Reset Scheme
3.5. Hardware Testing x
3.5.1. Test Procedure
4. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature x
4.1. Features 4.2. Hardware and Software Requirements 4.3. Functional Description 4.4. Simulation 4.5. Hardware Testing 4.6. Interface Signals 4.7. Configuration Registers
4.3. Functional Description x
4.3.1. Design Components 4.3.2. Clocking Scheme 4.3.3. Reset Scheme
4.4. Simulation x
4.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
4.5. Hardware Testing x
4.5.1. Test Procedure
5. 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature x
5.1. Features 5.2. Hardware and Software Requirements 5.3. Functional Description 5.4. Simulation 5.5. Hardware Testing 5.6. Interface Signals 5.7. Configuration Registers
5.3. Functional Description x
5.3.1. Design Components 5.3.2. Clocking Scheme 5.3.3. Reset Scheme
5.4. Simulation x
5.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
5.5. Hardware Testing x
5.5.1. Test Procedure
6. 2.5G Ethernet Design Example x
6.1. Features 6.2. Hardware and Software Requirements 6.3. Functional Description 6.4. Simulation 6.5. Hardware Testing 6.6. Interface Signals 6.7. Configuration Registers
6.3. Functional Description x
6.3.1. Design Components 6.3.2. Clocking Scheme 6.3.3. Reset Scheme
6.5. Hardware Testing x
6.5.1. Test Procedure
7. 2.5G Ethernet Design Example with IEEE 1588v2 Feature x
7.1. Features 7.2. Hardware and Software Requirements 7.3. Functional Description 7.4. Simulation 7.5. Hardware Testing 7.6. Interface Signals 7.7. Configuration Registers
7.3. Functional Description x
7.3.1. Design Components 7.3.2. Clocking Scheme 7.3.3. Reset Scheme
7.4. Simulation x
7.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
7.5. Hardware Testing x
7.5.1. Test Procedure
8. 10M/100M/1G/2.5G/10G MGE (Multi Gigabit Ethernet) PCS Only Ethernet Design Example x
8.1. Features 8.2. Hardware and Software Requirements 8.3. Functional Description 8.4. Simulation 8.5. Hardware Testing 8.6. Interface Signals 8.7. Configuration Registers
8.3. Functional Description x
8.3.1. Design Components 8.3.2. Clocking Scheme 8.3.3. Reset Scheme
8.5. Hardware Testing x
8.5.1. Test Procedure
9. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example x
9.1. Features 9.2. Hardware and Software Requirements 9.3. Functional Description 9.4. Simulation 9.5. Hardware Testing 9.6. Interface Signals 9.7. Configuration Registers
9.3. Functional Description x
9.3.1. Design Components 9.3.2. Clocking Scheme 9.3.3. Reset Scheme
9.5. Hardware Testing x
9.5.1. Test Procedure
10. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588v2 Feature x
10.1. Features 10.2. Hardware and Software Requirements 10.3. Functional Description 10.4. Simulation 10.5. Hardware Testing 10.6. Interface Signals
10.3. Functional Description x
10.3.1. Design Components 10.3.2. Clocking Scheme 10.3.3. Reset Scheme
10.4. Simulation x
10.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
10.5. Hardware Testing x
10.5.1. Test Procedure
11. Interface Signals Description x
11.1. Clock and Reset Interface Signals 11.2. Avalon® Memory-Mapped Interface Signals 11.3. Avalon® Streaming Interface Signals 11.4. PHY Interface Signals 11.5. Status Interface 11.6. IEEE 1588v2 Timestamp Interface Signals
12. Configuration Registers Description x
12.1. Register Access Definition 12.2. Low Latency Ethernet 10G MAC 12.3. PHY 12.4. Packet Generator and Traffic Monitor Register Map
12.3. PHY x
12.3.1. 1G/2.5G/5G/10G Multirate PHY
1. Quick Start Guide
2. 10M/100M/1G/2.5G Ethernet Design Example
3. 10M/100M/1G/2.5G/10G Ethernet Design Example
4. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
5. 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature
6. 2.5G Ethernet Design Example
7. 2.5G Ethernet Design Example with IEEE 1588v2 Feature
8. 10M/100M/1G/2.5G/10G MGE (Multi Gigabit Ethernet) PCS Only Ethernet Design Example
9. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
10. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588v2 Feature
11. Interface Signals Description
12. Configuration Registers Description
13. Low Latency Ethernet 10G MAC IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives
14. Document Revision History for the Low Latency Ethernet 10G MAC IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

1.5. Signal Tap Debugging

The IP provides a list of predefined debug signals to capture the behavior of the design example components.
To program the hardware design example on Agilex™ 5 devices:
  1. Click Tools > Signal Tap Logic Analyzer.
  2. Click Hardware Setup and select respective hardware for programming.
  3. Click on Scan Chain to select the proper JTAG.
  4. Click on the SOF Manager to browse and program the SOF.
  5. After the programming is complete, click any of the signals under the Setup window to view the signal behavior.
  6. In the Instance Manager toolbar, click Run Analysis. The signal capture and signal transitions is displayed in the Data window.
  7. Refer to the Signal Tap Logic Analyzer Introduction for more information about Signal Tap.
To start the signal tap debugging:
  1. Generate the design example for the Low Latency Ethernet 10G MAC IP.
  2. Open the .qpf file in the intel_eth_em10g32_0_EXAMPLE_DESIGN/LL10G_10G_*/ directory.
  3. In the Quartus® Prime Pro Edition software, click File > Open > <LL10G_*> > *.stp

Section Content
Signals Description
Signals List

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