F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide

ID 792946
Date 12/04/2023
Public
Document Table of Contents

7.3. Transceivers

The transceiver provides physical lane with the line rate of 25.78125 Gbps.
Table 10.  Transceiver Signals
Signal Direction Description
tx_serial Output TX transceiver signal. Each tx_serial bit becomes two physical pins that form a differential pair.
rx_serial Input RX transceiver signals. Each rx_serial bit becomes two physical pins that form a differential pair.