Visible to Intel only — GUID: pxe1699441116776
Ixiasoft
Visible to Intel only — GUID: pxe1699441116776
Ixiasoft
7.4. Transceiver Reconfiguration Signals
The core uses Ethernet F-Tile IP as a PMA (transceiver) for 100G. You can find more information about the Ethernet F-Tile IP core in the Ethernet F-Tile IP User Guide. The transceivers require an SYS PLL to generate the high speed serial clock. Only one SYS PLL is required for the transceivers within a single F-Tile. If required, you can share the SYS PLLs with other transceivers in the design. This is because the SYS PLL does not reside within the core and it must be instantiated externally. The example design instantiates the core and the SYS PLL.
Signal Name | Direction | Width | Description |
---|---|---|---|
reconfig_clk | Input | 1 | Avalon® clock. The clock frequency is 100 MHz.
Note: All transceiver reconfiguration interface signals are synchronous to reconfig_clk.
|
reconfig_reset | Input | 1 | Resets the Avalon® memory-mapped interface and all the registers to which it provides access. |
Lane 0 Ports | |||
i_reconfig_xcvr0_addr | Input | 18 | Address bus. |
i_reconfig_xcvr0_read | Input | 1 | Read enable signal. Signal is active high. |
i_reconfig_xcvr0_write | Input | 1 | Write enable signal. Signal is active high. |
i_reconfig_xcvr0_writedata | Input | 32 | A 32-bit data write bus. reconfig_address specifies the address. |
i_reconfig_xcvr0_byteenable | Input | 4 | Byte enable Signal. |
o_reconfig_xcvr0_readdata | Output | 32 | A 32-bit data read bus. Drives read data from the specified address. Signal is valid after reconfig_waitrequest is deasserted. |
o_reconfig_xcvr0_waitrequest | Output | 1 | Indicates the Avalon memory-mapped interface is busy. Keep the reconfig_write or reconfig_read asserted until reconfig_waitrequest is deasserted. |
o_reconfig_xcvr0_readdata_valid | Output | 1 | Indicates that the reconfig_readdata signal is valid. |
Port Name | Direction | Description |
---|---|---|
reconfig_eth_address[13:0] | Input | Address for the Ethernet control status registers. |
reconfig_eth_read | Input | Read request signal for the Ethernet control status registers. |
reconfig_eth_write | Input | Write request signal for the Ethernet control status registers. |
reconfig_eth_readdata[31:0] | Output | Reads data from this port when the reconfig_eth_read signal is asserted. |
reconfig_eth_writedata[31:0] | Input | Writes data to this port when the reconfig_eth_write signal is asserted. |
reconfig_eth_waitrequest | Output | Indicates that the control and status interface is busy and unable to respond to read or write requests. |
reconfig_eth_readdatavalid | Output | Indicates that the reconfig_eth_readdata signal is valid. |