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1. About the F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide
2. About this IP
3. Getting Started
4. F-Tile Low Latency 100G Ethernet Intel® FPGA IP Parameters
5. Functional Description
6. Reset
7. Interfaces and Signal Descriptions
8. Control, Status, and Statistics Register Descriptions
9. Document Revision History for the F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide
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5.1.3.3.2. RX CRC Checking and Dynamic Forwarding
The RX MAC checks the incoming CRC32 for errors. It asserts l1_rx_error[1] in the same cycle as l1_rx_endofpacket when it detects an error. CRC checking takes several cycles. The packet frame is delayed to align the CRC output with the end of the frame.
By default, the RX MAC strips off the CRC bytes before forwarding the packet to the MAC client. You can configure the core to retain the RX CRC and forward it to the client by updating the MAC_CRC_CONFIG register.