F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide
ID
792946
Date
12/04/2023
Public
A newer version of this document is available. Customers should click here to go to the newest version.
1. About the F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide
2. About this IP
3. Getting Started
4. F-Tile Low Latency 100G Ethernet Intel® FPGA IP Parameters
5. Functional Description
6. Reset
7. Interfaces and Signal Descriptions
8. Control, Status, and Statistics Register Descriptions
9. Document Revision History for the F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide
3.5.3. Placement Settings for the 100G Ethernet Intel FPGA IP Core
The Quartus Prime software provides the options to specify design partitions and Logic Lock (Standard) or Logic Lock regions for incremental compilation, to control placement on the device. To achieve timing closure for your design, you might need to provide floorplan guidelines using one or both of these features.
The appropriate floorplan is always design-specific, and depends on your design.
Related Information