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1. About the F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide
2. About this IP
3. Getting Started
4. F-Tile Low Latency 100G Ethernet Intel® FPGA IP Parameters
5. Functional Description
6. Reset
7. Interfaces and Signal Descriptions
8. Control, Status, and Statistics Register Descriptions
9. Document Revision History for the F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide
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5.1.3. F-Tile Low Latency 100G Ethernet Intel® FPGA IP Core RX MAC Datapath
The RX MAC receives Ethernet frames and forwards the payload with relevant header bytes to the client after performing some MAC functions on header bytes. The RX MAC processes all incoming valid frames.
Figure 10. Flow of Client Frame With Preamble Pass-Through Turned On This figure uses the following notational conventions:
- <p> = payload size, which is arbitrarily large.
- <s> = number of padding bytes (0–46).
Figure 11. Flow of Client Frame With Preamble Pass-Through Turned Off This figure uses the following notational conventions:
- <p> = payload size, which is arbitrarily large.
- <s> = number of padding bytes (0–46).
Figure 12. RX MAC Datapath