Intel® Simics® Simulator for Intel® FPGAs: User Guide

ID 784383
Date 12/04/2023

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5.5.3. Events

Intel® Simics® simulator is an event-driven simulator. Depending on the type of event, the resolution of them is different. Events are handled by event queues. An event is scheduled to occur in the future by adding this into a queue. There are different type queues with a specific resolution to handle these events.

Event Queue Notes
Time(PS) Resolution of 1 ps. Used by providers such as clocks or processors.
Step Resolution of a CPU step. Events are programmed to occur triggered on a CPU step.
Cycle Resolution of a CPU cycle. Events are programmed to occur triggered on a CPU cycle. These are the most common events.

Based on the queue resolution, the Intel® Simics® simulator evaluates (every step, cycle, and ps) if an event is ready to be triggered. If this is the case, the event is processed, and it is removed from the queue or rescheduled in the queue depending on how the event was configured.

Events with step resolution are useful for debugging (execute 1 step at a time, stop after executing 3 steps, and so on). Events with time resolution are rather independent from the flow of execution (sector read operation on the hard disk finishes in 1 ms).

# Intel Simics simulator CLI 

# Runing 5 steps using run command

simics> run 5 steps
Processor agilex.hps.core[0] is stalling - may take a long time to finish.
# Running 5 steps using stepi command

simics> stepi 5
[agilex.hps.core[0]] v:0xffff800008010a84 p:0x8000000002010a84  add sp, sp, x0
[agilex.hps.core[0]] v:0xffff800008010a88 p:0x8000000002010a88  sub x0, sp, x0
[agilex.hps.core[0]] v:0xffff800008010a8c p:0x8000000002010a8c  tbnz w0, #14, 0xffff800008010a9c
[agilex.hps.core[0]] v:0xffff800008010a90 p:0x8000000002010a90  sub x0, sp, x0
[agilex.hps.core[0]] v:0xffff800008010a94 p:0x8000000002010a94  sub sp, sp, x0
# Run 5 cycles using step-cycle command

simics> step-cycle 3
[agilex.hps.core[0]] v:0xffff800008011334 p:0x8000000002011334  stp x28, x29, [sp, #224]
[agilex.hps.core[0]] v:0xffff800008011338 p:0x8000000002011338  add x21, sp, #0x150
[agilex.hps.core[0]] v:0xffff80000801133c p:0x800000000201133c  mrs x28, sp_el0

In the case of events cycle resolution, events are triggered in the following order:

  • All events posted for this specific cycle, except step execution.
  • For each step scheduled for execution on this cycle.
  • All events scheduled for that specific step.
  • A step execution.

Events belonging to the same category are executed in FIFO order: posted first is executed first.

The step and cycle events posted by the device models can be observed with the print-event-queue as shown in the following capture. Under these categories, you can find the interrupts and exceptions.

# Intel Simics simulator CLI 

simics> print-event-queue
Cycle      Object             Description 
      46  agilex.hps.uart0    regs.xmit_proceed 
  915499  agilexhps.timer[0]  aarch64.cntp.timeout
39641472  agilex.phy0 
39649472  agilex.phy0

In the above capture, you can see that for each event in the list there is information about the number of cycles pending to trigger the event, the object that posted it and a brief description about it.