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1. FPGA AI Suite PCIe-based Design Example User Guide
2. About the PCIe* -based Design Example
3. Getting Started with the FPGA AI Suite PCIe* -based Design Example
4. Building the FPGA AI Suite Runtime
5. Running the Design Example Demonstration Applications
6. Design Example Components
7. Design Example System Architecture for the Intel PAC with Arria® 10 GX FPGA
A. FPGA AI Suite PCIe-based Design Example User Guide Archives
B. FPGA AI Suite PCIe-based Design Example User Guide Document Revision History
5.1. Exporting Trained Graphs from Source Frameworks
5.2. Compiling Exported Graphs Through the FPGA AI Suite
5.3. Compiling the PCIe* -based Example Design
5.4. Programming the FPGA Device ( Arria® 10)
5.5. Programming the FPGA Device ( Agilex™ 7)
5.6. Performing Accelerated Inference with the dla_benchmark Application
5.7. Running the Ported OpenVINO™ Demonstration Applications
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6.3. Software Components
The PCIe* -based design example contains a sample software stack for the runtime flow.
The following figure, Software Stacks for FPGA AI Suite Inference, shows the complete runtime stack.
For the Arria® 10 design example, the following components comprise the runtime stack:
- OpenVINO™ Toolkit 2022.3.1 LTS (Inference Engine, Heterogeneous Plugin)
- FPGA AI Suite runtime plugin
- OPAE driver 1.1.2-2
For the Agilex™ 7 design example, the following components comprise the runtime stack:
- OpenVINO™ Toolkit 2022.3.1 LTS (Inference Engine, Heterogeneous Plugin)
- FPGA AI Suite runtime plugin
- Terasic DE10-Agilex-B2E2 board driver
The PCIe* -based design example contains the source files and Makefiles to build the FPGA AI Suite runtime plugin. The other components, OpenVINO™ and OPAE, are external and must be manually pre-installed.
A separate flow compiles the AI network graph using the FPGA AI Suite compiler, as shown in figure Software Stacks for FPGA AI Suite Inference below as the Compilation Software Stack.
The compilation flow output is a single binary file called CompiledNetwork.bin that contains the compiled network partitions for FPGA and CPU devices along with the network weights. The network is compiled for a specific FPGA AI Suite architecture and batch size. This binary is created on-disk only when using the Ahead-Of-Time flow; when the JIT flow is used, the compiled object stays in-memory only.
An Architecture File describes the FPGA AI Suite IP architecture to the compiler. You must specify the same Architecture File to the FPGA AI Suite compiler and to the FPGA AI Suite PCIe Example Design build script (dla_build_example_design.py).
The runtime flow accepts the CompiledNetwork.bin file as the input network along with the image data files.
Figure 1. Software Stacks for FPGA AI Suite Inference
The runtime stack cannot program the FPGA with a bitstream. To build a bitstream and program the FPGA devices:
- Compile the design example. For details, refer to Compiling the PCIe* -based Design Example.
- Program the device with the bitstream. For details, refer to Programming the FPGA Device ( Arria 10) or Programming the FPGA Device ( Agilex 7) (depending on your FPGA device).
To run inference through the OpenVINO™ Toolkit on the FPGA, set the OpenVINO™ device configuration flag (used by the heterogeneous Plugin) to FPGA or HETERO:FPGA,CPU.