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1. FPGA AI Suite PCIe-based Design Example User Guide
2. About the PCIe* -based Design Example
3. Getting Started with the FPGA AI Suite PCIe* -based Design Example
4. Building the FPGA AI Suite Runtime
5. Running the Design Example Demonstration Applications
6. Design Example Components
7. Design Example System Architecture for the Intel PAC with Arria® 10 GX FPGA
A. FPGA AI Suite PCIe-based Design Example User Guide Archives
B. FPGA AI Suite PCIe-based Design Example User Guide Document Revision History
5.1. Exporting Trained Graphs from Source Frameworks
5.2. Compiling Exported Graphs Through the FPGA AI Suite
5.3. Compiling the PCIe* -based Example Design
5.4. Programming the FPGA Device ( Arria® 10)
5.5. Programming the FPGA Device ( Agilex™ 7)
5.6. Performing Accelerated Inference with the dla_benchmark Application
5.7. Running the Ported OpenVINO™ Demonstration Applications
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6.2. Example Architecture Bitstream Files
The FPGA AI Suite provides example Architecture Files and bitstreams for the PCIe* -based Example Design ( Arria® 10 and Agilex™ 7). The bitstreams are distributed as a separate tarball.