FPGA AI Suite: PCIe-based Design Example User Guide

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ID 768977
Date 3/29/2024
Public
Document Table of Contents
Document Table of Contents x
1. FPGA AI Suite PCIe-based Design Example User Guide 2. About the PCIe* -based Design Example 3. Getting Started with the FPGA AI Suite PCIe* -based Design Example 4. Building the FPGA AI Suite Runtime 5. Running the Design Example Demonstration Applications 6. Design Example Components 7. Design Example System Architecture for the Intel PAC with Arria® 10 GX FPGA A. FPGA AI Suite PCIe-based Design Example User Guide Archives B. FPGA AI Suite PCIe-based Design Example User Guide Document Revision History
4. Building the FPGA AI Suite Runtime x
4.1. CMake Targets 4.2. Build Options
5. Running the Design Example Demonstration Applications x
5.1. Exporting Trained Graphs from Source Frameworks 5.2. Compiling Exported Graphs Through the FPGA AI Suite 5.3. Compiling the PCIe* -based Example Design 5.4. Programming the FPGA Device ( Arria® 10) 5.5. Programming the FPGA Device ( Agilex™ 7) 5.6. Performing Accelerated Inference with the dla_benchmark Application 5.7. Running the Ported OpenVINO™ Demonstration Applications
5.6. Performing Accelerated Inference with the dla_benchmark Application x
5.6.1. Inference on Image Classification Graphs 5.6.2. Inference on Object Detection Graphs 5.6.3. Additional dla_benchmark Options
5.6.2. Inference on Object Detection Graphs x
5.6.2.1. The mAP and COCO AP Metrics 5.6.2.2. Specifying Ground Truth 5.6.2.3. Example of Inference on Object Detection Graphs
5.7. Running the Ported OpenVINO™ Demonstration Applications x
5.7.1. Example Running the Object Detection Demonstration Application
6. Design Example Components x
6.1. Build Script 6.2. Example Architecture Bitstream Files 6.3. Software Components 6.4. Software Interface to the BSP
6.1. Build Script x
6.1.1. Build Script Options 6.1.2. Script Flow
6.3. Software Components x
6.3.1. OpenVINO™ FPGA Runtime Plugin 6.3.2. FPGA AI Suite Runtime 6.3.3. BSP Driver
7. Design Example System Architecture for the Intel PAC with Arria® 10 GX FPGA x
7.1. System Overview 7.2. Hardware
7.2. Hardware x
7.2.1. PLL Adjustment
1. FPGA AI Suite PCIe-based Design Example User Guide
2. About the PCIe* -based Design Example
3. Getting Started with the FPGA AI Suite PCIe* -based Design Example
4. Building the FPGA AI Suite Runtime
5. Running the Design Example Demonstration Applications
6. Design Example Components
7. Design Example System Architecture for the Intel PAC with Arria® 10 GX FPGA
A. FPGA AI Suite PCIe-based Design Example User Guide Archives
B. FPGA AI Suite PCIe-based Design Example User Guide Document Revision History

7. Design Example System Architecture for the Intel PAC with Arria® 10 GX FPGA

The Intel PAC with Arria® 10 GX FPGA design example is derived from the OpenCL BSP provided with the Intel Acceleration Stack for Intel® Xeon® CPU with FPGAs (which also includes OPAE technology).

The Intel Acceleration Stack is designed to make FPGAs usable as accelerators. On the FPGA side, the Intel Acceleration Stack splits acceleration functions into two parts:

  • The FPGA interface manager (FIM) is FPGA hardware that contains the FPGA interface unit (FIU) and external interfaces for functions like memory access and networking. The FIM is locked and cannot be changed. The FIM is sometimes referred to as BBS, blue bits, or blue bitstream.
  • The accelerator function (AF) is a compiled accelerator image implemented in FPGA logic that accelerates an application. AFs are compiled from accelerator functional units (AFUs). An AFU and associated AFs are sometimes referred to as GBS, green bits, or green bitstream. An FPGA device can be reprogrammed while leaving the FIM in place.

The FIM handles external interfaces to the host, to which it is connected via PCIe. On the host side, a driver stack communicates with the AFU via the FIM. This is referred to as OPAE (Open Programmable Acceleration Engine). OPAE talks to the AFU with the CCI-P (core cache interface) protocol that provides an abstraction over PCIe protocol.


Section Content
System Overview
Hardware

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