FPGA AI Suite: PCIe-based Design Example User Guide

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ID 768977
Date 3/29/2024
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Document Table of Contents
Document Table of Contents x
1. FPGA AI Suite PCIe-based Design Example User Guide 2. About the PCIe* -based Design Example 3. Getting Started with the FPGA AI Suite PCIe* -based Design Example 4. Building the FPGA AI Suite Runtime 5. Running the Design Example Demonstration Applications 6. Design Example Components 7. Design Example System Architecture for the Intel PAC with Arria® 10 GX FPGA A. FPGA AI Suite PCIe-based Design Example User Guide Archives B. FPGA AI Suite PCIe-based Design Example User Guide Document Revision History
4. Building the FPGA AI Suite Runtime x
4.1. CMake Targets 4.2. Build Options
5. Running the Design Example Demonstration Applications x
5.1. Exporting Trained Graphs from Source Frameworks 5.2. Compiling Exported Graphs Through the FPGA AI Suite 5.3. Compiling the PCIe* -based Example Design 5.4. Programming the FPGA Device ( Arria® 10) 5.5. Programming the FPGA Device ( Agilex™ 7) 5.6. Performing Accelerated Inference with the dla_benchmark Application 5.7. Running the Ported OpenVINO™ Demonstration Applications
5.6. Performing Accelerated Inference with the dla_benchmark Application x
5.6.1. Inference on Image Classification Graphs 5.6.2. Inference on Object Detection Graphs 5.6.3. Additional dla_benchmark Options
5.6.2. Inference on Object Detection Graphs x
5.6.2.1. The mAP and COCO AP Metrics 5.6.2.2. Specifying Ground Truth 5.6.2.3. Example of Inference on Object Detection Graphs
5.7. Running the Ported OpenVINO™ Demonstration Applications x
5.7.1. Example Running the Object Detection Demonstration Application
6. Design Example Components x
6.1. Build Script 6.2. Example Architecture Bitstream Files 6.3. Software Components 6.4. Software Interface to the BSP
6.1. Build Script x
6.1.1. Build Script Options 6.1.2. Script Flow
6.3. Software Components x
6.3.1. OpenVINO™ FPGA Runtime Plugin 6.3.2. FPGA AI Suite Runtime 6.3.3. BSP Driver
7. Design Example System Architecture for the Intel PAC with Arria® 10 GX FPGA x
7.1. System Overview 7.2. Hardware
7.2. Hardware x
7.2.1. PLL Adjustment
1. FPGA AI Suite PCIe-based Design Example User Guide
2. About the PCIe* -based Design Example
3. Getting Started with the FPGA AI Suite PCIe* -based Design Example
4. Building the FPGA AI Suite Runtime
5. Running the Design Example Demonstration Applications
6. Design Example Components
7. Design Example System Architecture for the Intel PAC with Arria® 10 GX FPGA
A. FPGA AI Suite PCIe-based Design Example User Guide Archives
B. FPGA AI Suite PCIe-based Design Example User Guide Document Revision History

4.2. Build Options

The runtime folder in the design example package contains a script to build the runtime called build_runtime.sh.
Issue the following command to run the script: 
./build_runtime.sh <command_line_options>
Where <command_line_options> are defined in the following table:
Table 2.  Command Line Options for the build_runtime.sh Script
Command Description
-h | --help Show usage details
--cmake_debug Call cmake with a debug flag
--verbosity=<number> Large numbers add some extra verbosity
--build_dir=<path> Directory where the runtime build should be placed
--disable_jit

If this flag is specified, then the runtime will only support the Ahead of Time mode. The runtime will not link to the precompiled compiler libraries.

Use this mode when trying to compile the runtime on an unsupported operating system.
--build_demo Adds several OpenVINO™ demo applications to the runtime build. The demo applications are in subdirectories of the runtime/directory.
--de10_agilex Target the Terasic* DE10-Agilex Development Board.

If this option is not specified, then the runtime will by default target the Intel® PAC with Arria® 10 GX FPGA.

--aot_splitter_example Builds the AOT splitter example utility for the selected target ( Intel® PAC with Arria® 10 GX FPGA or Terasic* DE10-Agilex Development Board).

This option builds an AOT file for a model, splits the AOT file into its constituent components (weights, overlay instructions, etc), and the builds a small utility that loads the model and a single image onto the target FPGA board without using OpenVINO™ .

You must set the $AOT_SPLITTER_EXAMPLE_MODEL and $AOT_SPLITTER_EXAMPLE_INPUT environment variables correctly. For details, refer to " FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility Example Application" in FPGA AI Suite IP Reference Manual .

The FPGA AI Suite runtime plugin is built in release mode by default. To enable debug mode, you must specify the -cmake_debug option of the script command.

The -no_make option skips the final call to the make command. You can make this call manually instead.

FPGA AI Suite hardware is compiled to include one or more IP instances, with the same architecture for all instances. Each instance accesses data from a unique bank of DDR:

  • An Intel® Programmable Acceleration Card (PAC) with Arria® 10 GX FPGA has two DDR banks and supports two instances.
  • The Terasic* DE10-Agilex Development Board supports up to four instances.

The runtime automatically adapts to the correct number of instances.

If the FPGA AI Suite runtime uses two or more instances, then the image batches are divided between the instances to execute two or more batches in parallel on the FPGA device.

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