FPGA AI Suite: PCIe-based Design Example User Guide

ID 768977
Date 3/29/2024
Document Table of Contents

7.2.1. PLL Adjustment

The design example build script adjusts the PLL driving the FPGA AI Suite IP clock based on the fMAX that the Quartus® Prime compiler achieves.

A fully rigorous production-quality flow would re-run timing analysis after the PLL adjustment to account for the small possibility that change in PLL frequency might cause a change in clock characteristics (for example, jitter) that cause a timing failure. A production design that shares the FPGA AI Suite IP clock with other system components might target a fixed frequency and skip PLL adjustment