3. Intel® FPGA AI Suite IP Generation Utility
The Intel® FPGA AI Suite IP generation utility reads an input Architecture Description File (.arch) and places generated IP into an IP library that can be imported into Platform Designer or used directly in a pure RTL design. The generated IP is configured based on the Architecture Description (.arch) File, which defines the following items:
- Top RTL parameters are set to reflect values in the Architecture Description File
- The Discovery ROM MIF is created to specify an architecture hash and Intel® FPGA AI Suite compiler version string
The generation utility also copies all the required RTL files into a single directory. As convenience options, the utility can also help to create .qsf files and wrappers for the PCIe Example Design or to compile an instance of the IP with a dummy BSP interface.
- Unlicensed IP
- The unlicensed IP has a limit of 10000 inferences. After 10000 inferences, the unlicensed IP refuses to perform any additional inference and a bit in the CSR is set. For details about the CSR bit, refer to DMA Descriptor Queue.
- Licensed IP
- The licensed IP has no inference limitation
You can use either licensed and unlicensed IP for bitstream generation so that you can fully test your design during the evaluation process.