126.96.36.199. Input Scale and Shift
Many graphs require that input data be pre-scaled and pre-shifted. These scale and shift operations are supported in the Intel® FPGA AI Suite IP if they are sent to the device. Depending on the folding options specified, the method of support differs for the Intel® FPGA AI Suite IP. Input preprocessing is not supported for 5D inputs.
For the ExternalFullFolding or ExternalFullExtraPEFolding options, external modules of the Intel® FPGA AI Suite are responsible for replacing the zero padding of the input data with non-zero shift values received as input from the Intel® FPGA AI Suite compiler.
For the NoFolding or PEFolding options, the scaling and shifting are performed entirely by the Intel® FPGA AI Suite IP without any additional support from the host or external modules. If the scale and shift operation is not mapped to the device, then it is typically performed as an operation fused with the conversion to FP16. This fused operation is performed either by a host CPU or by an external hardware block.