2.5.5. Output Tensor In-Memory Format
The output tensor in-memory format is similar to the input tensor in-memory format described in Input Feature Tensor In-Memory Format. However, the output tensor is padded to the nearest multiple of KVEC rather than CVEC, with the padding being done at the boundaries between Intel® FPGA AI Suite IP outputs rather than strictly at the edge of the logical tensor output.
While the logical tensor output might be a single tensor, the Intel® FPGA AI Suite IP might compute this output as one single output or by slicing the output into smaller pieces.
To enable the plugin to determine the appropriate output layout and offsets, the compiler provides a DlaRuntimeOutputConfiguration object. One of the fields of this object is the output_tensor_mapping field, which provides a mapping from Intel® FPGA AI Suite IP tensor output to logical tensor output.
This file describes the tensor shape and offsets.
This file shows the element-wise mapping of the Intel® FPGA AI Suite output tensor to the logical output tensor. This mapping is in the inverse of the input mapping described in Input Transform Mapping. Refer to the example in that topic for a description of the transform mapping CSV file.