Intel® FPGA AI Suite: IP Reference Manual

ID 768974
Date 9/06/2023

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Document Table of Contents

B. Intel® FPGA AI Suite IP Reference Manual Document Revision History

Document Version Intel® FPGA AI SuiteVersion Changes
2023.09.08 2023.2.1
  • Added Multilayer Perceptrons (MLPs) to supported models.
2023.07.03 2023.2
  • Updated "Model Performance" with Version 2023.2 values and the enabling of non-default Intel® Quartus® Prime options (register merging).
  • Added additional information about modifying the internal precision of a graph for performance improvement in "Architecture Description File Format for Instance Parameterization".
2023.04.05 2023.1
  • Added ChannelToSpace, DepthToSpace, and PixelShuffle to " Intel® FPGA AI Suite Layer / Primitive Ranges".
  • Added enable_debug to " Intel® FPGA AI Suite IP Block Configuration and Interfaces".
  • Added description of enable_round_clamp activation parameter where needed.
  • Added "Input Transform Mapping".
  • Added output transform mapping information to "Output Tensor In-Memory Format".
  • Renamed thedlac command. The Intel® FPGA AI Suite compiler command is now dla_compiler.
  • Updated "Model Performance" with Version 2023.1 values.
  • Updated the Intel® Agilex™ product family name to "Intel Agilex® 7."
2023.02.03 2022.2
  • Correct the description of the -bgr option of the AOT splitter utility.
2022.12.23 2022.2
  • Added SqueezeNet to the list of supported models.
  • Added the family architecture description file global parameter.
  • Removed the --family IP generation utility command option.



  • Removed references to HLS generation.
  • Updated descriptions of parameters in the .arch file.
  • Added a Model Performance section.



  • Added information for Intel® Agilex™device support.
  • Added information for MobileNet v3 support.



  • Various corrections and updates.



  • Renamed Intel® FPGA AI Suite IP Core to Intel® FPGA AI Suite IP".



  • Initial release.