Intel® FPGA AI Suite: IP Reference Manual

ID 768974
Date 9/06/2023
Public

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2.5.4.4. Input Transform Mapping

To help make sense of how input data is transformed for a compiled graph, the Intel® FPGA AI Suite compiler creates the following CSV files:
  • input_transform_dump_<graph-name>.csv

    This file describes the tensor shape, padding, and stride for each input tensor.

  • input_transform_mapping_<graph-name>.csv

    This file shows the element-wise mapping of the logical input tensor elements (domain) to the Intel FPGA AI Suite IP input tensor format (co-domain) described earlier.

The transform mapping file has columns that correspond to the offset and subscript indices for the logical input tensor elements, and the corresponding elements in the transformed Intel® FPGA AI Suite input tensor.
For a graph with the input example given in Input Tensor In-Memory Layout, the transform mapping CSV output from the DLA compiler would be as follows:
Table 6.  Example Transform Mapping CSV Output
Logical Tensor Offset Input Channel (C) Input Depth (D) Input Height (H) Input Width (W) Input Tensor Offset Transformed Channel (C) Transformed Depth (D) Transformed Height (H) Transformed Width (W) Transformed C-vector (Cvec)
0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 1 2 0 0 0 1 0
2 0 0 1 0 4 0 0 1 0 0
3 0 0 1 1 6 0 0 1 1 0
4 1 0 0 0 1 1 0 0 0 0
5 1 0 0 1 3 1 0 0 1 0
6 1 0 1 0 5 1 0 1 0 0
7 1 0 1 1 7 1 0 1 1 0
8 2 0 0 0 8 0 0 0 0 1
9 2 0 0 1 10 0 0 0 1 1
10 2 0 1 0 12 0 0 1 0 1
11 2 0 1 1 14 0 0 1 1 1

The tensor offsets in this table are logical, not address offsets and are thus independent of data type. The transformation typically implicitly adds zero padding to the data. As such, not all transformed output logical offsets are mapped from a given input logical offset.