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1. About the F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide
2. About this IP
3. Getting Started
4. F-Tile Low Latency 50G Ethernet Intel® FPGA IP Parameters
5. Functional Description
6. Reset
7. Interfaces and Signal Descriptions
8. Control, Status, and Statistics Register Descriptions
9. Document Revision History for the F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide
Visible to Intel only — GUID: rzs1667870145062
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7.3. Transceivers
The transceiver provides physical lane with the line rate of 25.78125 Gbps.
Signal |
Direction |
Description |
---|---|---|
O_tx_serial | Output | TX transceiver signal. Each tx_serial bit becomes two physical pins that form a differential pair. |
i_rx_serial | Input | RX transceiver signals. Each rx_serial bit becomes two physical pins that form a differential pair. |